drivers/iio/adc/ad4695.c
Source file repositories/reference/linux-study-clean/drivers/iio/adc/ad4695.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/iio/adc/ad4695.c- Extension
.c- Size
- 56088 bytes
- Lines
- 2020
- Domain
- Driver Families
- Bucket
- drivers/iio
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/align.hlinux/bitfield.hlinux/bits.hlinux/compiler.hlinux/delay.hlinux/device.hlinux/err.hlinux/gpio/consumer.hlinux/iio/buffer-dmaengine.hlinux/iio/buffer.hlinux/iio/iio.hlinux/iio/triggered_buffer.hlinux/iio/trigger_consumer.hlinux/minmax.hlinux/mutex.hlinux/property.hlinux/pwm.hlinux/regmap.hlinux/regulator/consumer.hlinux/spi/offload/consumer.hlinux/spi/offload/provider.hlinux/spi/spi.hlinux/units.hdt-bindings/iio/adc/adi,ad4695.h
Detected Declarations
struct ad4695_chip_infostruct ad4695_channel_configstruct ad4695_stateenum ad4695_in_pairfunction ad4695_regmap_bus_reg_writefunction ad4695_regmap_bus_reg_readfunction ad4695_cnv_manual_triggerfunction ad4695_set_single_cycle_modefunction ad4695_enter_advanced_sequencer_modefunction ad4695_exit_conversion_modefunction ad4695_set_ref_voltagefunction ad4695_osr_to_regvalfunction ad4695_write_chn_cfgfunction ad4695_buffer_preenablefunction iio_for_each_active_channelfunction modefunction ad4695_buffer_postdisablefunction ad4695_trigger_handlerfunction ad4695_offload_buffer_postenablefunction iio_for_each_active_channelfunction ad4695_offload_buffer_predisablefunction scoped_guardfunction ad4695_read_one_samplefunction __ad4695_read_info_rawfunction ad4695_read_rawfunction ad4695_write_raw_get_fmtfunction ad4695_set_osr_valfunction ad4695_get_calibbiasfunction __ad4695_write_rawfunction ad4695_write_rawfunction ad4695_read_availfunction ad4695_debugfs_reg_accessfunction ad4695_get_current_scan_typefunction ad4695_parse_channel_cfgfunction ad4695_offload_trigger_matchfunction ad4695_offload_trigger_requestfunction ad4695_offload_trigger_validatefunction ad4695_pwm_disablefunction ad4695_probe_spi_offloadfunction ad4695_probe
Annotated Snippet
struct ad4695_chip_info {
const char *name;
int max_sample_rate;
u32 t_acq_ns;
u8 num_voltage_inputs;
};
struct ad4695_channel_config {
unsigned int channel;
bool highz_en;
bool bipolar;
enum ad4695_in_pair pin_pairing;
unsigned int common_mode_mv;
unsigned int oversampling_ratio;
};
struct ad4695_state {
struct spi_device *spi;
struct spi_offload *offload;
struct spi_offload_trigger *offload_trigger;
struct regmap *regmap;
struct regmap *regmap16;
struct gpio_desc *reset_gpio;
/* currently PWM CNV only supported with SPI offload use */
struct pwm_device *cnv_pwm;
/* protects against concurrent use of cnv_pwm */
struct mutex cnv_pwm_lock;
/* offload also requires separate gpio to manually control CNV */
struct gpio_desc *cnv_gpio;
/* voltages channels plus temperature and timestamp */
struct iio_chan_spec iio_chan[AD4695_MAX_VIN_CHANNELS + 2];
struct ad4695_channel_config channels_cfg[AD4695_MAX_VIN_CHANNELS];
const struct ad4695_chip_info *chip_info;
int sample_freq_range[3];
/* Reference voltage. */
unsigned int vref_mv;
/* Common mode input pin voltage. */
unsigned int com_mv;
/*
* 2 per voltage and temperature chan plus 1 xfer to trigger 1st
* CNV. Excluding the trigger xfer, every 2nd xfer only serves
* to control CS and add a delay between the last SCLK and next
* CNV rising edges.
*/
struct spi_transfer buf_read_xfer[AD4695_MAX_VIN_CHANNELS * 2 + 3];
struct spi_message buf_read_msg;
/* Raw conversion data received. */
IIO_DECLARE_DMA_BUFFER_WITH_TS(u16, buf, AD4695_MAX_VIN_CHANNELS + 1);
u16 raw_data;
/* Commands to send for single conversion. */
u16 cnv_cmd;
u8 cnv_cmd2;
/* Buffer for storing data from regmap bus reads/writes */
u8 regmap_bus_data[4];
};
static const struct regmap_range ad4695_regmap_rd_ranges[] = {
regmap_reg_range(AD4695_REG_SPI_CONFIG_A, AD4695_REG_SPI_CONFIG_B),
regmap_reg_range(AD4695_REG_DEVICE_TYPE, AD4695_REG_DEVICE_TYPE),
regmap_reg_range(AD4695_REG_SCRATCH_PAD, AD4695_REG_SCRATCH_PAD),
regmap_reg_range(AD4695_REG_VENDOR_L, AD4695_REG_LOOP_MODE),
regmap_reg_range(AD4695_REG_SPI_CONFIG_C, AD4695_REG_SPI_STATUS),
regmap_reg_range(AD4695_REG_STATUS, AD4695_REG_ALERT_STATUS2),
regmap_reg_range(AD4695_REG_CLAMP_STATUS, AD4695_REG_CLAMP_STATUS),
regmap_reg_range(AD4695_REG_SETUP, AD4695_REG_AC_CTRL),
regmap_reg_range(AD4695_REG_GPIO_CTRL, AD4695_REG_TEMP_CTRL),
regmap_reg_range(AD4695_REG_CONFIG_IN(0), AD4695_REG_CONFIG_IN(15)),
regmap_reg_range(AD4695_REG_AS_SLOT(0), AD4695_REG_AS_SLOT(127)),
};
static const struct regmap_access_table ad4695_regmap_rd_table = {
.yes_ranges = ad4695_regmap_rd_ranges,
.n_yes_ranges = ARRAY_SIZE(ad4695_regmap_rd_ranges),
};
static const struct regmap_range ad4695_regmap_wr_ranges[] = {
regmap_reg_range(AD4695_REG_SPI_CONFIG_A, AD4695_REG_SPI_CONFIG_B),
regmap_reg_range(AD4695_REG_SCRATCH_PAD, AD4695_REG_SCRATCH_PAD),
regmap_reg_range(AD4695_REG_LOOP_MODE, AD4695_REG_LOOP_MODE),
regmap_reg_range(AD4695_REG_SPI_CONFIG_C, AD4695_REG_SPI_STATUS),
regmap_reg_range(AD4695_REG_SETUP, AD4695_REG_AC_CTRL),
regmap_reg_range(AD4695_REG_GPIO_CTRL, AD4695_REG_TEMP_CTRL),
regmap_reg_range(AD4695_REG_CONFIG_IN(0), AD4695_REG_CONFIG_IN(15)),
regmap_reg_range(AD4695_REG_AS_SLOT(0), AD4695_REG_AS_SLOT(127)),
};
static const struct regmap_access_table ad4695_regmap_wr_table = {
.yes_ranges = ad4695_regmap_wr_ranges,
.n_yes_ranges = ARRAY_SIZE(ad4695_regmap_wr_ranges),
};
Annotation
- Immediate include surface: `linux/align.h`, `linux/bitfield.h`, `linux/bits.h`, `linux/compiler.h`, `linux/delay.h`, `linux/device.h`, `linux/err.h`, `linux/gpio/consumer.h`.
- Detected declarations: `struct ad4695_chip_info`, `struct ad4695_channel_config`, `struct ad4695_state`, `enum ad4695_in_pair`, `function ad4695_regmap_bus_reg_write`, `function ad4695_regmap_bus_reg_read`, `function ad4695_cnv_manual_trigger`, `function ad4695_set_single_cycle_mode`, `function ad4695_enter_advanced_sequencer_mode`, `function ad4695_exit_conversion_mode`.
- Atlas domain: Driver Families / drivers/iio.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.