drivers/iio/adc/ad7768-1.c

Source file repositories/reference/linux-study-clean/drivers/iio/adc/ad7768-1.c

File Facts

System
Linux kernel
Corpus path
drivers/iio/adc/ad7768-1.c
Extension
.c
Size
54444 bytes
Lines
1954
Domain
Driver Families
Bucket
drivers/iio
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ad7768_chip_info {
	const char *name;
	const struct iio_chan_spec *channel_spec;
	int num_channels;
	const int *pga_gains;
	int num_pga_modes;
	int default_pga_mode;
	int pgia_mode2pin_offset;
	bool has_pga;
	bool has_variable_aaf;
	bool has_vcm_regulator;
};

struct ad7768_state {
	struct spi_device *spi;
	struct spi_offload *offload;
	struct spi_offload_trigger *offload_trigger;
	struct regmap *regmap;
	struct regmap *regmap24;
	int vref_uv;
	struct regulator_dev *vcm_rdev;
	unsigned int vcm_output_sel;
	struct clk *mclk;
	unsigned int mclk_freq;
	unsigned int oversampling_ratio;
	enum ad7768_filter_type filter_type;
	unsigned int samp_freq;
	unsigned int samp_freq_avail[ARRAY_SIZE(ad7768_mclk_div_rates)];
	unsigned int samp_freq_avail_len;
	unsigned int pga_gain_mode;
	unsigned int aaf_gain;
	int scale_tbl[ADAQ776X_MAX_GAIN_MODES][2];
	struct completion completion;
	struct iio_trigger *trig;
	struct gpio_descs *pga_gpios;
	struct gpio_desc *gpio_sync_in;
	struct gpio_desc *gpio_reset;
	const char *labels[AD7768_MAX_CHANNELS];
	struct gpio_chip gpiochip;
	struct spi_transfer offload_xfer;
	struct spi_message offload_msg;
	const struct ad7768_chip_info *chip;
	bool en_spi_sync;
	struct mutex pga_lock; /* protect device internal state (PGA) */
	/*
	 * DMA (thus cache coherency maintenance) may require the
	 * transfer buffers to live in their own cache lines.
	 */
	union {
		struct {
			__be32 chan;
			aligned_s64 timestamp;
		} scan;
		__be32 d32;
		u8 d8[2];
	} data __aligned(IIO_DMA_MINALIGN);
};

static const struct regmap_range ad7768_regmap_rd_ranges[] = {
	regmap_reg_range(AD7768_REG_CHIP_TYPE, AD7768_REG_CHIP_GRADE),
	regmap_reg_range(AD7768_REG_SCRATCH_PAD, AD7768_REG_SCRATCH_PAD),
	regmap_reg_range(AD7768_REG_VENDOR_L, AD7768_REG_VENDOR_H),
	regmap_reg_range(AD7768_REG_INTERFACE_FORMAT, AD7768_REG_GAIN_LO),
	regmap_reg_range(AD7768_REG_SPI_DIAG_ENABLE, AD7768_REG_DIG_DIAG_ENABLE),
	regmap_reg_range(AD7768_REG_MASTER_STATUS, AD7768_REG_COEFF_CONTROL),
	regmap_reg_range(AD7768_REG_ACCESS_KEY, AD7768_REG_ACCESS_KEY),
};

static const struct regmap_access_table ad7768_regmap_rd_table = {
	.yes_ranges = ad7768_regmap_rd_ranges,
	.n_yes_ranges = ARRAY_SIZE(ad7768_regmap_rd_ranges),
};

static const struct regmap_range ad7768_regmap_wr_ranges[] = {
	regmap_reg_range(AD7768_REG_SCRATCH_PAD, AD7768_REG_SCRATCH_PAD),
	regmap_reg_range(AD7768_REG_INTERFACE_FORMAT, AD7768_REG_GPIO_WRITE),
	regmap_reg_range(AD7768_REG_OFFSET_HI, AD7768_REG_GAIN_LO),
	regmap_reg_range(AD7768_REG_SPI_DIAG_ENABLE, AD7768_REG_DIG_DIAG_ENABLE),
	regmap_reg_range(AD7768_REG_SPI_DIAG_STATUS, AD7768_REG_SPI_DIAG_STATUS),
	regmap_reg_range(AD7768_REG_COEFF_CONTROL, AD7768_REG_COEFF_CONTROL),
	regmap_reg_range(AD7768_REG_ACCESS_KEY, AD7768_REG_ACCESS_KEY),
};

static const struct regmap_access_table ad7768_regmap_wr_table = {
	.yes_ranges = ad7768_regmap_wr_ranges,
	.n_yes_ranges = ARRAY_SIZE(ad7768_regmap_wr_ranges),
};

static const struct regmap_config ad7768_regmap_config = {
	.name = "ad7768-1-8",

Annotation

Implementation Notes