drivers/iio/adc/max1027.c
Source file repositories/reference/linux-study-clean/drivers/iio/adc/max1027.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/iio/adc/max1027.c- Extension
.c- Size
- 16832 bytes
- Lines
- 637
- Domain
- Driver Families
- Bucket
- drivers/iio
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/module.hlinux/mod_devicetable.hlinux/spi/spi.hlinux/delay.hlinux/iio/iio.hlinux/iio/buffer.hlinux/iio/trigger.hlinux/iio/trigger_consumer.hlinux/iio/triggered_buffer.h
Detected Declarations
struct max1027_chip_infostruct max1027_stateenum max1027_idfunction max1027_wait_eocfunction max1027_configure_chans_and_startfunction max1027_enable_triggerfunction max1027_read_single_valuefunction max1027_read_rawfunction max1027_debugfs_reg_accessfunction max1027_set_cnvst_trigger_statefunction max1027_read_scanfunction max1027_handlerfunction max1027_trigger_handlerfunction max1027_probe
Annotated Snippet
struct max1027_chip_info {
const struct iio_chan_spec *channels;
unsigned int num_channels;
const unsigned long *available_scan_masks;
};
static const struct max1027_chip_info max1027_chip_info_tbl[] = {
[max1027] = {
.channels = max1027_channels,
.num_channels = ARRAY_SIZE(max1027_channels),
.available_scan_masks = max1027_available_scan_masks,
},
[max1029] = {
.channels = max1029_channels,
.num_channels = ARRAY_SIZE(max1029_channels),
.available_scan_masks = max1029_available_scan_masks,
},
[max1031] = {
.channels = max1031_channels,
.num_channels = ARRAY_SIZE(max1031_channels),
.available_scan_masks = max1031_available_scan_masks,
},
[max1227] = {
.channels = max1227_channels,
.num_channels = ARRAY_SIZE(max1227_channels),
.available_scan_masks = max1027_available_scan_masks,
},
[max1229] = {
.channels = max1229_channels,
.num_channels = ARRAY_SIZE(max1229_channels),
.available_scan_masks = max1029_available_scan_masks,
},
[max1231] = {
.channels = max1231_channels,
.num_channels = ARRAY_SIZE(max1231_channels),
.available_scan_masks = max1031_available_scan_masks,
},
};
struct max1027_state {
const struct max1027_chip_info *info;
struct spi_device *spi;
struct iio_trigger *trig;
__be16 *buffer;
struct mutex lock;
struct completion complete;
u8 reg __aligned(IIO_DMA_MINALIGN);
};
static int max1027_wait_eoc(struct iio_dev *indio_dev)
{
struct max1027_state *st = iio_priv(indio_dev);
unsigned int conversion_time = MAX1027_CONVERSION_UDELAY;
int ret;
if (st->spi->irq) {
ret = wait_for_completion_timeout(&st->complete,
msecs_to_jiffies(1000));
reinit_completion(&st->complete);
if (!ret)
return -ETIMEDOUT;
} else {
if (indio_dev->active_scan_mask)
conversion_time *= hweight32(*indio_dev->active_scan_mask);
usleep_range(conversion_time, conversion_time * 2);
}
return 0;
}
/* Scan from chan 0 to the highest requested channel. Include temperature on demand. */
static int max1027_configure_chans_and_start(struct iio_dev *indio_dev)
{
struct max1027_state *st = iio_priv(indio_dev);
st->reg = MAX1027_CONV_REG | MAX1027_SCAN_0_N;
st->reg |= MAX1027_CHAN(fls(*indio_dev->active_scan_mask) - 2);
if (*indio_dev->active_scan_mask & MAX1X27_SCAN_MASK_TEMP)
st->reg |= MAX1027_TEMP;
return spi_write(st->spi, &st->reg, 1);
}
static int max1027_enable_trigger(struct iio_dev *indio_dev, bool enable)
{
struct max1027_state *st = iio_priv(indio_dev);
st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2;
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/module.h`, `linux/mod_devicetable.h`, `linux/spi/spi.h`, `linux/delay.h`, `linux/iio/iio.h`, `linux/iio/buffer.h`, `linux/iio/trigger.h`.
- Detected declarations: `struct max1027_chip_info`, `struct max1027_state`, `enum max1027_id`, `function max1027_wait_eoc`, `function max1027_configure_chans_and_start`, `function max1027_enable_trigger`, `function max1027_read_single_value`, `function max1027_read_raw`, `function max1027_debugfs_reg_access`, `function max1027_set_cnvst_trigger_state`.
- Atlas domain: Driver Families / drivers/iio.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.