drivers/iio/adc/nxp-sar-adc.c

Source file repositories/reference/linux-study-clean/drivers/iio/adc/nxp-sar-adc.c

File Facts

System
Linux kernel
Corpus path
drivers/iio/adc/nxp-sar-adc.c
Extension
.c
Size
27306 bytes
Lines
1035
Domain
Driver Families
Bucket
drivers/iio
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct nxp_sar_adc {
	void __iomem *regs;
	phys_addr_t regs_phys;
	u8 current_channel;
	u8 channels_used;
	u16 value;
	u32 vref_mV;

	/* Save and restore context. */
	u32 inpsamp;
	u32 pwdn;

	struct clk *clk;
	struct dma_chan	*dma_chan;
	struct completion completion;
	struct circ_buf dma_buf;

	dma_addr_t rx_dma_buf;
	dma_cookie_t cookie;

	/* Protect circular buffers access. */
	spinlock_t lock;

	/* Array of enabled channels. */
	u16 buffered_chan[NXP_SAR_ADC_NR_CHANNELS];

	/* Buffer to be filled by the DMA. */
	IIO_DECLARE_BUFFER_WITH_TS(u16, buffer, NXP_SAR_ADC_NR_CHANNELS);
};

struct nxp_sar_adc_data {
	u32 vref_mV;
	const char *model;
};

#define ADC_CHAN(_idx, _chan_type) {				\
	.type = (_chan_type),					\
	.indexed = 1,						\
	.channel = (_idx),					\
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |	\
				BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
	.scan_index = (_idx),					\
	.scan_type = {						\
		.sign = 'u',					\
		.realbits = 12,					\
		.storagebits = 16,				\
	},							\
}

static const struct iio_chan_spec nxp_sar_adc_iio_channels[] = {
	ADC_CHAN(0, IIO_VOLTAGE),
	ADC_CHAN(1, IIO_VOLTAGE),
	ADC_CHAN(2, IIO_VOLTAGE),
	ADC_CHAN(3, IIO_VOLTAGE),
	ADC_CHAN(4, IIO_VOLTAGE),
	ADC_CHAN(5, IIO_VOLTAGE),
	ADC_CHAN(6, IIO_VOLTAGE),
	ADC_CHAN(7, IIO_VOLTAGE),
	/*
	 * The NXP SAR ADC documentation marks the channels 8 to 31 as
	 * "Reserved". Reflect the same in the driver in case new ADC
	 * variants comes with more channels.
	 */
	IIO_CHAN_SOFT_TIMESTAMP(32),
};

static void nxp_sar_adc_irq_cfg(struct nxp_sar_adc *info, bool enable)
{
	if (enable)
		writel(NXP_SAR_ADC_ISR_ECH, NXP_SAR_ADC_IMR(info->regs));
	else
		writel(0, NXP_SAR_ADC_IMR(info->regs));
}

static void nxp_sar_adc_wait_for(struct nxp_sar_adc *info, unsigned int cycles)
{
	u64 rate;

	rate = clk_get_rate(info->clk);
	if (rate)
		ndelay(div64_u64(NSEC_PER_SEC, rate * cycles));
}

static bool nxp_sar_adc_set_enabled(struct nxp_sar_adc *info, bool enable)
{
	u32 mcr;
	bool pwdn;

	mcr = readl(NXP_SAR_ADC_MCR(info->regs));

Annotation

Implementation Notes