drivers/iio/adc/qcom-spmi-iadc.c
Source file repositories/reference/linux-study-clean/drivers/iio/adc/qcom-spmi-iadc.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/iio/adc/qcom-spmi-iadc.c- Extension
.c- Size
- 13512 bytes
- Lines
- 587
- Domain
- Driver Families
- Bucket
- drivers/iio
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitops.hlinux/completion.hlinux/delay.hlinux/err.hlinux/iio/iio.hlinux/interrupt.hlinux/kernel.hlinux/mutex.hlinux/module.hlinux/of.hlinux/platform_device.hlinux/regmap.hlinux/slab.h
Detected Declarations
struct iadc_chipfunction iadc_readfunction iadc_writefunction iadc_resetfunction iadc_set_statefunction iadc_status_showfunction iadc_configurefunction iadc_poll_wait_eocfunction iadc_read_resultfunction iadc_do_conversionfunction iadc_read_rawfunction iadc_isrfunction iadc_update_offsetfunction iadc_version_checkfunction iadc_rsense_readfunction iadc_probe
Annotated Snippet
struct iadc_chip {
struct regmap *regmap;
struct device *dev;
u16 base;
bool poll_eoc;
u32 rsense[2];
u16 offset[2];
u16 gain;
struct mutex lock;
struct completion complete;
};
static int iadc_read(struct iadc_chip *iadc, u16 offset, u8 *data)
{
unsigned int val;
int ret;
ret = regmap_read(iadc->regmap, iadc->base + offset, &val);
if (ret < 0)
return ret;
*data = val;
return 0;
}
static int iadc_write(struct iadc_chip *iadc, u16 offset, u8 data)
{
return regmap_write(iadc->regmap, iadc->base + offset, data);
}
static int iadc_reset(struct iadc_chip *iadc)
{
u8 data;
int ret;
ret = iadc_write(iadc, IADC_SEC_ACCESS, IADC_SEC_ACCESS_DATA);
if (ret < 0)
return ret;
ret = iadc_read(iadc, IADC_PERH_RESET_CTL3, &data);
if (ret < 0)
return ret;
ret = iadc_write(iadc, IADC_SEC_ACCESS, IADC_SEC_ACCESS_DATA);
if (ret < 0)
return ret;
data |= IADC_FOLLOW_WARM_RB;
return iadc_write(iadc, IADC_PERH_RESET_CTL3, data);
}
static int iadc_set_state(struct iadc_chip *iadc, bool state)
{
return iadc_write(iadc, IADC_EN_CTL1, state ? IADC_EN_CTL1_SET : 0);
}
static void iadc_status_show(struct iadc_chip *iadc)
{
u8 mode, sta1, chan, dig, en, req;
int ret;
ret = iadc_read(iadc, IADC_MODE_CTL, &mode);
if (ret < 0)
return;
ret = iadc_read(iadc, IADC_DIG_PARAM, &dig);
if (ret < 0)
return;
ret = iadc_read(iadc, IADC_CH_SEL_CTL, &chan);
if (ret < 0)
return;
ret = iadc_read(iadc, IADC_CONV_REQ, &req);
if (ret < 0)
return;
ret = iadc_read(iadc, IADC_STATUS1, &sta1);
if (ret < 0)
return;
ret = iadc_read(iadc, IADC_EN_CTL1, &en);
if (ret < 0)
return;
dev_err(iadc->dev,
"mode:%02x en:%02x chan:%02x dig:%02x req:%02x sta1:%02x\n",
mode, en, chan, dig, req, sta1);
}
Annotation
- Immediate include surface: `linux/bitops.h`, `linux/completion.h`, `linux/delay.h`, `linux/err.h`, `linux/iio/iio.h`, `linux/interrupt.h`, `linux/kernel.h`, `linux/mutex.h`.
- Detected declarations: `struct iadc_chip`, `function iadc_read`, `function iadc_write`, `function iadc_reset`, `function iadc_set_state`, `function iadc_status_show`, `function iadc_configure`, `function iadc_poll_wait_eoc`, `function iadc_read_result`, `function iadc_do_conversion`.
- Atlas domain: Driver Families / drivers/iio.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.