drivers/iio/adc/rohm-bd79112.c

Source file repositories/reference/linux-study-clean/drivers/iio/adc/rohm-bd79112.c

File Facts

System
Linux kernel
Corpus path
drivers/iio/adc/rohm-bd79112.c
Extension
.c
Size
15402 bytes
Lines
552
Domain
Driver Families
Bucket
drivers/iio
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct bd79112_data {
	struct spi_device *spi;
	struct regmap *map;
	struct device *dev;
	struct gpio_chip gc;
	unsigned long gpio_valid_mask;
	unsigned int vref_mv;
	struct spi_transfer read_xfer[2];
	struct spi_transfer write_xfer;
	struct spi_message read_msg;
	struct spi_message write_msg;
	/* 16-bit TX, valid data in high byte */
	u8 read_tx[2] __aligned(IIO_DMA_MINALIGN);
	/* 8-bit address followed by 8-bit data */
	u8 reg_write_tx[2];
	/* 12-bit of ADC data or 8 bit of reg data */
	__be16 read_rx;
};

/*
 * The ADC data is read issuing SPI-command matching the channel number.
 * We treat this as a register address.
 */
#define BD79112_REG_AGIO0A		0x00
#define BD79112_REG_AGIO15B		0x1f

/*
 * ADC STATUS_FLAG appended to ADC data will be set, if the ADC result is being
 * read for a channel, which input pin is muxed to be a GPIO.
 */
#define BD79112_ADC_STATUS_FLAG BIT(14)

/*
 * The BD79112 requires "R/W bit" to be set for SPI register (not ADC data)
 * reads and an "IOSET bit" to be set for read/write operations (which aren't
 * reading the ADC data).
 */
#define BD79112_BIT_RW			BIT(4)
#define BD79112_BIT_IO			BIT(5)

#define BD79112_REG_GPI_VALUE_B8_15	(BD79112_BIT_IO | 0x0)
#define BD79112_REG_GPI_VALUE_B0_B7	(BD79112_BIT_IO | 0x1)
#define BD79112_REG_GPI_VALUE_A8_15	(BD79112_BIT_IO | 0x2)
#define BD79112_REG_GPI_VALUE_A0_A7	(BD79112_BIT_IO | 0x3)

#define BD79112_REG_GPI_EN_B7_B15	(BD79112_BIT_IO | 0x4)
#define BD79112_REG_GPI_EN_B0_B7	(BD79112_BIT_IO | 0x5)
#define BD79112_REG_GPI_EN_A8_A15	(BD79112_BIT_IO | 0x6)
#define BD79112_REG_GPI_EN_A0_A7	(BD79112_BIT_IO | 0x7)

#define BD79112_REG_GPO_EN_B7_B15	(BD79112_BIT_IO | 0x8)
#define BD79112_REG_GPO_EN_B0_B7	(BD79112_BIT_IO | 0x9)
#define BD79112_REG_GPO_EN_A8_A15	(BD79112_BIT_IO | 0xa)
#define BD79112_REG_GPO_EN_A0_A7	(BD79112_BIT_IO | 0xb)

#define BD79112_NUM_GPIO_EN_REGS	8
#define BD79112_FIRST_GPIO_EN_REG	BD79112_REG_GPI_EN_B7_B15

#define BD79112_REG_GPO_VALUE_B8_15	(BD79112_BIT_IO | 0xc)
#define BD79112_REG_GPO_VALUE_B0_B7	(BD79112_BIT_IO | 0xd)
#define BD79112_REG_GPO_VALUE_A8_15	(BD79112_BIT_IO | 0xe)
#define BD79112_REG_GPO_VALUE_A0_A7	(BD79112_BIT_IO | 0xf)

#define BD79112_REG_MAX BD79112_REG_GPO_VALUE_A0_A7

/*
 * Read transaction consists of two 16-bit sequences separated by CSB.
 * For register read, 'IOSET' bit must be set. For ADC read, IOSET is cleared
 * and ADDR equals the channel number (0 ... 31).
 *
 * First 16-bit sequence, MOSI as below, MISO data ignored:
 * - SCK: | 1 | 2 |   3   |    4   | 5 .. 8 | 9 .. 16 |
 * - MOSI:| 0 | 0 | IOSET | RW (1) |  ADDR  |  8'b0   |
 *
 * CSB released and re-acquired between these sequences
 *
 * Second 16-bit sequence, MISO as below, MOSI data ignored:
 *   For Register read data is 8 bits:
 *   - SCK: | 1 .. 8 |   9 .. 16   |
 *   - MISO:|  8'b0  | 8-bit data  |
 *
 *   For ADC read data is 12 bits:
 *   - SCK: | 1 |      2      | 3  4 |   4 .. 16   |
 *   - MISO:| 0 | STATUS_FLAG | 2'b0 | 12-bit data |
 *     The 'STATUS_FLAG' is set if the read input pin was configured as a GPIO.
 */
static int bd79112_reg_read(void *context, unsigned int reg, unsigned int *val)
{
	struct bd79112_data *data = context;
	int ret;

Annotation

Implementation Notes