drivers/iio/adc/ti-adc081c.c
Source file repositories/reference/linux-study-clean/drivers/iio/adc/ti-adc081c.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/iio/adc/ti-adc081c.c- Extension
.c- Size
- 5705 bytes
- Lines
- 238
- Domain
- Driver Families
- Bucket
- drivers/iio
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/err.hlinux/i2c.hlinux/module.hlinux/mod_devicetable.hlinux/property.hlinux/iio/iio.hlinux/iio/buffer.hlinux/iio/trigger_consumer.hlinux/iio/triggered_buffer.hlinux/regulator/consumer.h
Detected Declarations
struct adc081cstruct adcxx1c_modelfunction adc081c_read_rawfunction adc081c_trigger_handlerfunction adc081c_reg_disablefunction adc081c_probe
Annotated Snippet
struct adc081c {
struct i2c_client *i2c;
struct regulator *ref;
/* 8, 10 or 12 */
int bits;
/* Ensure natural alignment of buffer elements */
struct {
u16 channel;
aligned_s64 ts;
} scan;
};
#define REG_CONV_RES 0x00
static int adc081c_read_raw(struct iio_dev *iio,
struct iio_chan_spec const *channel, int *value,
int *shift, long mask)
{
struct adc081c *adc = iio_priv(iio);
int err;
switch (mask) {
case IIO_CHAN_INFO_RAW:
err = i2c_smbus_read_word_swapped(adc->i2c, REG_CONV_RES);
if (err < 0)
return err;
*value = (err & 0xFFF) >> (12 - adc->bits);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
err = regulator_get_voltage(adc->ref);
if (err < 0)
return err;
*value = err / 1000;
*shift = adc->bits;
return IIO_VAL_FRACTIONAL_LOG2;
default:
break;
}
return -EINVAL;
}
#define ADCxx1C_CHAN(_bits) { \
.type = IIO_VOLTAGE, \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.scan_type = { \
.sign = 'u', \
.realbits = (_bits), \
.storagebits = 16, \
.shift = 12 - (_bits), \
.endianness = IIO_CPU, \
}, \
}
#define DEFINE_ADCxx1C_CHANNELS(_name, _bits) \
static const struct iio_chan_spec _name ## _channels[] = { \
ADCxx1C_CHAN((_bits)), \
IIO_CHAN_SOFT_TIMESTAMP(1), \
}; \
#define ADC081C_NUM_CHANNELS 2
struct adcxx1c_model {
const struct iio_chan_spec* channels;
int bits;
};
DEFINE_ADCxx1C_CHANNELS(adc081c, 8);
DEFINE_ADCxx1C_CHANNELS(adc101c, 10);
DEFINE_ADCxx1C_CHANNELS(adc121c, 12);
static const struct adcxx1c_model adc081c_model = {
.channels = adc081c_channels,
.bits = 8,
};
static const struct adcxx1c_model adc101c_model = {
.channels = adc101c_channels,
.bits = 10,
};
static const struct adcxx1c_model adc121c_model = {
Annotation
- Immediate include surface: `linux/err.h`, `linux/i2c.h`, `linux/module.h`, `linux/mod_devicetable.h`, `linux/property.h`, `linux/iio/iio.h`, `linux/iio/buffer.h`, `linux/iio/trigger_consumer.h`.
- Detected declarations: `struct adc081c`, `struct adcxx1c_model`, `function adc081c_read_raw`, `function adc081c_trigger_handler`, `function adc081c_reg_disable`, `function adc081c_probe`.
- Atlas domain: Driver Families / drivers/iio.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.