drivers/iio/adc/ti-ads1018.c
Source file repositories/reference/linux-study-clean/drivers/iio/adc/ti-ads1018.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/iio/adc/ti-ads1018.c- Extension
.c- Size
- 20187 bytes
- Lines
- 740
- Domain
- Driver Families
- Bucket
- drivers/iio
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/array_size.hlinux/bitfield.hlinux/bitmap.hlinux/dev_printk.hlinux/gpio/consumer.hlinux/interrupt.hlinux/math.hlinux/mod_devicetable.hlinux/module.hlinux/spi/spi.hlinux/types.hlinux/units.hasm/byteorder.hlinux/iio/buffer.hlinux/iio/iio.hlinux/iio/trigger.hlinux/iio/trigger_consumer.hlinux/iio/triggered_buffer.h
Detected Declarations
struct ads1018_chan_datastruct ads1018_chip_infostruct ads1018function BITfunction ads1018_calc_delayfunction ads1018_spi_read_exclusivefunction ads1018_single_shotfunction ads1018_read_raw_direct_modefunction ads1018_read_rawfunction ads1018_read_availfunction ads1018_write_raw_direct_modefunction ads1018_write_rawfunction ads1018_write_raw_get_fmtfunction ads1018_set_trigger_enablefunction ads1018_set_trigger_disablefunction ads1018_set_trigger_statefunction ads1018_buffer_preenablefunction ads1018_buffer_postdisablefunction ads1018_irq_handlerfunction ads1018_trigger_handlerfunction ads1018_trigger_setupfunction ads1018_spi_probe
Annotated Snippet
struct ads1018_chan_data {
u8 pga_mode;
u8 data_rate_mode;
};
struct ads1018_chip_info {
const char *name;
const struct iio_chan_spec *channels;
unsigned long num_channels;
/* IIO_VAL_INT */
const u32 *data_rate_mode_to_hz;
unsigned long num_data_rate_mode_to_hz;
/*
* Let `res` be the chip's resolution and `fsr` (millivolts) be the
* full-scale range corresponding to the PGA mode given by the array
* index. Then, the gain is calculated using the following formula:
*
* gain = |fsr| / 2^(res - 1)
*
* This value then has to be represented in IIO_VAL_INT_PLUS_NANO
* format. For example if:
*
* gain = 6144 / 2^(16 - 1) = 0.1875
*
* ...then the formatted value is:
*
* { 0, 187500000 }
*/
const u32 pga_mode_to_gain[ADS1018_NUM_PGA_MODES][2];
/* IIO_VAL_INT_PLUS_MICRO */
const u32 temp_scale[2];
};
struct ads1018 {
struct spi_device *spi;
struct iio_trigger *indio_trig;
struct gpio_desc *drdy_gpiod;
int drdy_irq;
struct ads1018_chan_data chan_data[ADS1018_CHANNELS_MAX];
const struct ads1018_chip_info *chip_info;
struct spi_message msg_read;
struct spi_transfer xfer;
__be16 tx_buf[2] __aligned(IIO_DMA_MINALIGN);
__be16 rx_buf[2];
};
#define ADS1018_VOLT_DIFF_CHAN(_index, _chan, _chan2, _realbits) { \
.type = IIO_VOLTAGE, \
.channel = _chan, \
.channel2 = _chan2, \
.scan_index = _index, \
.scan_type = { \
.sign = 's', \
.realbits = _realbits, \
.storagebits = 16, \
.shift = 16 - _realbits, \
.endianness = IIO_BE, \
}, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.indexed = true, \
.differential = true, \
}
#define ADS1018_VOLT_CHAN(_index, _chan, _realbits) { \
.type = IIO_VOLTAGE, \
.channel = _chan, \
.scan_index = _index, \
.scan_type = { \
.sign = 's', \
.realbits = _realbits, \
.storagebits = 16, \
.shift = 16 - _realbits, \
.endianness = IIO_BE, \
}, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.indexed = true, \
Annotation
- Immediate include surface: `linux/array_size.h`, `linux/bitfield.h`, `linux/bitmap.h`, `linux/dev_printk.h`, `linux/gpio/consumer.h`, `linux/interrupt.h`, `linux/math.h`, `linux/mod_devicetable.h`.
- Detected declarations: `struct ads1018_chan_data`, `struct ads1018_chip_info`, `struct ads1018`, `function BIT`, `function ads1018_calc_delay`, `function ads1018_spi_read_exclusive`, `function ads1018_single_shot`, `function ads1018_read_raw_direct_mode`, `function ads1018_read_raw`, `function ads1018_read_avail`.
- Atlas domain: Driver Families / drivers/iio.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.