drivers/iio/adc/xilinx-ams.c
Source file repositories/reference/linux-study-clean/drivers/iio/adc/xilinx-ams.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/iio/adc/xilinx-ams.c- Extension
.c- Size
- 39339 bytes
- Lines
- 1451
- Domain
- Driver Families
- Bucket
- drivers/iio
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bits.hlinux/bitfield.hlinux/clk.hlinux/delay.hlinux/devm-helpers.hlinux/interrupt.hlinux/io.hlinux/iopoll.hlinux/kernel.hlinux/module.hlinux/mod_devicetable.hlinux/overflow.hlinux/platform_device.hlinux/property.hlinux/slab.hlinux/iio/events.hlinux/iio/iio.h
Detected Declarations
struct amsenum ams_alarm_bitenum ams_seqenum ams_ps_pl_seqfunction BITfunction ams_ps_update_regfunction ams_pl_update_regfunction ams_update_intrmaskfunction ams_disable_all_alarmsfunction ams_update_ps_alarmfunction ams_update_pl_alarmfunction ams_unmaskfunction ams_update_alarmfunction ams_enable_channel_sequencefunction ams_init_devicefunction ams_read_labelfunction ams_enable_single_channelfunction ams_read_vcc_regfunction ams_get_ps_scalefunction ams_get_pl_scalefunction ams_get_ctrl_scalefunction ams_read_rawfunction ams_get_alarm_offsetfunction ams_get_alarm_maskfunction ams_read_event_configfunction ams_write_event_configfunction ams_read_event_valuefunction ams_write_event_valuefunction ams_handle_eventfunction ams_handle_eventsfunction ams_unmask_workerfunction ams_irqfunction ams_get_ext_chanfunction fwnode_for_each_child_nodefunction ams_iounmap_psfunction ams_iounmap_plfunction ams_init_modulefunction ams_parse_firmwarefunction device_for_each_child_node_scopedfunction ams_probefunction ams_suspendfunction ams_resume
Annotated Snippet
struct ams {
void __iomem *base;
void __iomem *ps_base;
void __iomem *pl_base;
struct clk *clk;
struct device *dev;
struct mutex lock;
spinlock_t intr_lock;
unsigned int alarm_mask;
unsigned int current_masked_alarm;
u64 intr_mask;
struct delayed_work ams_unmask_work;
};
static inline void ams_ps_update_reg(struct ams *ams, unsigned int offset,
u32 mask, u32 data)
{
u32 val, regval;
val = readl(ams->ps_base + offset);
regval = (val & ~mask) | (data & mask);
writel(regval, ams->ps_base + offset);
}
static inline void ams_pl_update_reg(struct ams *ams, unsigned int offset,
u32 mask, u32 data)
{
u32 val, regval;
val = readl(ams->pl_base + offset);
regval = (val & ~mask) | (data & mask);
writel(regval, ams->pl_base + offset);
}
static void ams_update_intrmask(struct ams *ams, u64 mask, u64 val)
{
u32 regval;
ams->intr_mask = (ams->intr_mask & ~mask) | (val & mask);
regval = ~(ams->intr_mask | ams->current_masked_alarm);
writel(regval, ams->base + AMS_IER_0);
regval = ~(FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask));
writel(regval, ams->base + AMS_IER_1);
regval = ams->intr_mask | ams->current_masked_alarm;
writel(regval, ams->base + AMS_IDR_0);
regval = FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask);
writel(regval, ams->base + AMS_IDR_1);
}
static void ams_disable_all_alarms(struct ams *ams)
{
/* disable PS module alarm */
if (ams->ps_base) {
ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK,
AMS_REGCFG1_ALARM_MASK);
ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK,
AMS_REGCFG3_ALARM_MASK);
}
/* disable PL module alarm */
if (ams->pl_base) {
ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK,
AMS_REGCFG1_ALARM_MASK);
ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK,
AMS_REGCFG3_ALARM_MASK);
}
}
static void ams_update_ps_alarm(struct ams *ams, unsigned long alarm_mask)
{
u32 cfg;
u32 val;
val = FIELD_GET(AMS_ISR0_ALARM_2_TO_0_MASK, alarm_mask);
cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_2_TO_0_MASK, val));
val = FIELD_GET(AMS_ISR0_ALARM_6_TO_3_MASK, alarm_mask);
cfg &= ~(FIELD_PREP(AMS_CONF1_ALARM_6_TO_3_MASK, val));
ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg);
val = FIELD_GET(AMS_ISR0_ALARM_12_TO_7_MASK, alarm_mask);
cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_12_TO_7_MASK, val));
ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg);
}
Annotation
- Immediate include surface: `linux/bits.h`, `linux/bitfield.h`, `linux/clk.h`, `linux/delay.h`, `linux/devm-helpers.h`, `linux/interrupt.h`, `linux/io.h`, `linux/iopoll.h`.
- Detected declarations: `struct ams`, `enum ams_alarm_bit`, `enum ams_seq`, `enum ams_ps_pl_seq`, `function BIT`, `function ams_ps_update_reg`, `function ams_pl_update_reg`, `function ams_update_intrmask`, `function ams_disable_all_alarms`, `function ams_update_ps_alarm`.
- Atlas domain: Driver Families / drivers/iio.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.