drivers/iio/chemical/bme680_spi.c
Source file repositories/reference/linux-study-clean/drivers/iio/chemical/bme680_spi.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/iio/chemical/bme680_spi.c- Extension
.c- Size
- 3890 bytes
- Lines
- 160
- Domain
- Driver Families
- Bucket
- drivers/iio
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/mod_devicetable.hlinux/module.hlinux/regmap.hlinux/spi/spi.hbme680.h
Detected Declarations
struct bme680_spi_bus_contextfunction bme680_regmap_spi_select_pagefunction bme680_regmap_spi_writefunction bme680_regmap_spi_readfunction bme680_spi_probe
Annotated Snippet
struct bme680_spi_bus_context {
struct spi_device *spi;
u8 current_page;
};
/*
* In SPI mode there are only 7 address bits, a "page" register determines
* which part of the 8-bit range is active. This function looks at the address
* and writes the page selection bit if needed
*/
static int bme680_regmap_spi_select_page(
struct bme680_spi_bus_context *ctx, u8 reg)
{
struct spi_device *spi = ctx->spi;
int ret;
u8 buf[2];
u8 page = (reg & 0x80) ? 0 : 1; /* Page "1" is low range */
if (page == ctx->current_page)
return 0;
/*
* Data sheet claims we're only allowed to change bit 4, so we must do
* a read-modify-write on each and every page select
*/
buf[0] = BME680_REG_STATUS;
ret = spi_write_then_read(spi, buf, 1, buf + 1, 1);
if (ret < 0) {
dev_err(&spi->dev, "failed to set page %u\n", page);
return ret;
}
buf[0] = BME680_REG_STATUS;
if (page)
buf[1] |= BME680_SPI_MEM_PAGE_BIT;
else
buf[1] &= ~BME680_SPI_MEM_PAGE_BIT;
ret = spi_write(spi, buf, 2);
if (ret < 0) {
dev_err(&spi->dev, "failed to set page %u\n", page);
return ret;
}
ctx->current_page = page;
return 0;
}
static int bme680_regmap_spi_write(void *context, const void *data,
size_t count)
{
struct bme680_spi_bus_context *ctx = context;
struct spi_device *spi = ctx->spi;
int ret;
u8 buf[2];
memcpy(buf, data, 2);
ret = bme680_regmap_spi_select_page(ctx, buf[0]);
if (ret)
return ret;
/*
* The SPI register address (= full register address without bit 7)
* and the write command (bit7 = RW = '0')
*/
buf[0] &= ~0x80;
return spi_write(spi, buf, 2);
}
static int bme680_regmap_spi_read(void *context, const void *reg,
size_t reg_size, void *val, size_t val_size)
{
struct bme680_spi_bus_context *ctx = context;
struct spi_device *spi = ctx->spi;
int ret;
u8 addr = *(const u8 *)reg;
ret = bme680_regmap_spi_select_page(ctx, addr);
if (ret)
return ret;
addr |= 0x80; /* bit7 = RW = '1' */
return spi_write_then_read(spi, &addr, 1, val, val_size);
}
static const struct regmap_bus bme680_regmap_bus = {
Annotation
- Immediate include surface: `linux/mod_devicetable.h`, `linux/module.h`, `linux/regmap.h`, `linux/spi/spi.h`, `bme680.h`.
- Detected declarations: `struct bme680_spi_bus_context`, `function bme680_regmap_spi_select_page`, `function bme680_regmap_spi_write`, `function bme680_regmap_spi_read`, `function bme680_spi_probe`.
- Atlas domain: Driver Families / drivers/iio.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.