drivers/iio/dac/rohm-bd79703.c
Source file repositories/reference/linux-study-clean/drivers/iio/dac/rohm-bd79703.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/iio/dac/rohm-bd79703.c- Extension
.c- Size
- 6765 bytes
- Lines
- 247
- Domain
- Driver Families
- Bucket
- drivers/iio
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bits.hlinux/device.hlinux/module.hlinux/regmap.hlinux/regulator/consumer.hlinux/spi/spi.hlinux/iio/iio.h
Detected Declarations
struct bd79703_datastruct bd7970x_chip_datafunction bd79703_read_rawfunction bd79703_write_rawfunction bd79703_probe
Annotated Snippet
struct bd79703_data {
struct regmap *regmap;
int vfs;
};
/* Static, IC type specific data for different variants */
struct bd7970x_chip_data {
const char *name;
const struct iio_chan_spec *channels;
int num_channels;
bool has_vfs;
};
static int bd79703_read_raw(struct iio_dev *idev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct bd79703_data *data = iio_priv(idev);
if (mask != IIO_CHAN_INFO_SCALE)
return -EINVAL;
*val = data->vfs / 1000;
*val2 = BD79703_DAC_BITS;
return IIO_VAL_FRACTIONAL_LOG2;
}
static int bd79703_write_raw(struct iio_dev *idev,
struct iio_chan_spec const *chan, int val,
int val2, long mask)
{
struct bd79703_data *data = iio_priv(idev);
if (val < 0 || val >= 1 << BD79703_DAC_BITS)
return -EINVAL;
return regmap_write(data->regmap, chan->address, val);
};
static const struct iio_info bd79703_info = {
.read_raw = bd79703_read_raw,
.write_raw = bd79703_write_raw,
};
#define BD79703_CHAN_ADDR(_chan, _addr) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = (_chan), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.address = (_addr), \
}
#define BD79703_CHAN(_chan) BD79703_CHAN_ADDR((_chan), (_chan) + 1)
static const struct iio_chan_spec bd79700_channels[] = {
BD79703_CHAN(0),
BD79703_CHAN(1),
};
static const struct iio_chan_spec bd79701_channels[] = {
BD79703_CHAN(0),
BD79703_CHAN(1),
BD79703_CHAN(2),
};
/*
* The BD79702 has 4 channels. They aren't mapped to BD79703 channels 0, 1, 2
* and 3, but to the channels 0, 1, 4, 5. So the addressing used with SPI
* accesses is 1, 2, 5 and 6 for them. Thus, they're not constant offset to
* the channel number as with other IC variants.
*/
static const struct iio_chan_spec bd79702_channels[] = {
BD79703_CHAN_ADDR(0, 1),
BD79703_CHAN_ADDR(1, 2),
BD79703_CHAN_ADDR(2, 5),
BD79703_CHAN_ADDR(3, 6),
};
static const struct iio_chan_spec bd79703_channels[] = {
BD79703_CHAN(0),
BD79703_CHAN(1),
BD79703_CHAN(2),
BD79703_CHAN(3),
BD79703_CHAN(4),
BD79703_CHAN(5),
};
Annotation
- Immediate include surface: `linux/bits.h`, `linux/device.h`, `linux/module.h`, `linux/regmap.h`, `linux/regulator/consumer.h`, `linux/spi/spi.h`, `linux/iio/iio.h`.
- Detected declarations: `struct bd79703_data`, `struct bd7970x_chip_data`, `function bd79703_read_raw`, `function bd79703_write_raw`, `function bd79703_probe`.
- Atlas domain: Driver Families / drivers/iio.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.