drivers/iio/imu/inv_mpu6050/inv_mpu_aux.h
Source file repositories/reference/linux-study-clean/drivers/iio/imu/inv_mpu6050/inv_mpu_aux.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/iio/imu/inv_mpu6050/inv_mpu_aux.h- Extension
.h- Size
- 479 bytes
- Lines
- 20
- Domain
- Driver Families
- Bucket
- drivers/iio
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
inv_mpu_iio.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef INV_MPU_AUX_H_
#define INV_MPU_AUX_H_
#include "inv_mpu_iio.h"
int inv_mpu_aux_init(const struct inv_mpu6050_state *st);
int inv_mpu_aux_read(const struct inv_mpu6050_state *st, uint8_t addr,
uint8_t reg, uint8_t *val, size_t size);
int inv_mpu_aux_write(const struct inv_mpu6050_state *st, uint8_t addr,
uint8_t reg, uint8_t val);
#endif /* INV_MPU_AUX_H_ */
Annotation
- Immediate include surface: `inv_mpu_iio.h`.
- Atlas domain: Driver Families / drivers/iio.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.