drivers/iio/potentiometer/x9250.c
Source file repositories/reference/linux-study-clean/drivers/iio/potentiometer/x9250.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/iio/potentiometer/x9250.c- Extension
.c- Size
- 5194 bytes
- Lines
- 221
- Domain
- Driver Families
- Bucket
- drivers/iio
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/delay.hlinux/gpio/consumer.hlinux/iio/iio.hlinux/limits.hlinux/module.hlinux/regulator/consumer.hlinux/slab.hlinux/spi/spi.h
Detected Declarations
struct x9250_cfgstruct x9250enum x9250_typefunction x9250_write8function x9250_read8function x9250_read_rawfunction x9250_read_availfunction x9250_write_rawfunction x9250_probe
Annotated Snippet
struct x9250_cfg {
const char *name;
int kohms;
};
struct x9250 {
struct spi_device *spi;
const struct x9250_cfg *cfg;
struct gpio_desc *wp_gpio;
};
#define X9250_ID 0x50
#define X9250_CMD_RD_WCR(_p) (0x90 | (_p))
#define X9250_CMD_WR_WCR(_p) (0xa0 | (_p))
static int x9250_write8(struct x9250 *x9250, u8 cmd, u8 val)
{
u8 txbuf[3];
txbuf[0] = X9250_ID;
txbuf[1] = cmd;
txbuf[2] = val;
return spi_write_then_read(x9250->spi, txbuf, ARRAY_SIZE(txbuf), NULL, 0);
}
static int x9250_read8(struct x9250 *x9250, u8 cmd, u8 *val)
{
u8 txbuf[2];
txbuf[0] = X9250_ID;
txbuf[1] = cmd;
return spi_write_then_read(x9250->spi, txbuf, ARRAY_SIZE(txbuf), val, 1);
}
#define X9250_CHANNEL(ch) { \
.type = IIO_RESISTANCE, \
.indexed = 1, \
.output = 1, \
.channel = (ch), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_RAW), \
}
static const struct iio_chan_spec x9250_channels[] = {
X9250_CHANNEL(0),
X9250_CHANNEL(1),
X9250_CHANNEL(2),
X9250_CHANNEL(3),
};
static int x9250_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct x9250 *x9250 = iio_priv(indio_dev);
int ch = chan->channel;
int ret;
u8 v;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = x9250_read8(x9250, X9250_CMD_RD_WCR(ch), &v);
if (ret)
return ret;
*val = v;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = 1000 * x9250->cfg->kohms;
*val2 = U8_MAX;
return IIO_VAL_FRACTIONAL;
}
return -EINVAL;
}
static int x9250_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
const int **vals, int *type, int *length, long mask)
{
static const int range[] = {0, 1, 255}; /* min, step, max */
switch (mask) {
case IIO_CHAN_INFO_RAW:
*length = ARRAY_SIZE(range);
*vals = range;
*type = IIO_VAL_INT;
return IIO_AVAIL_RANGE;
}
Annotation
- Immediate include surface: `linux/delay.h`, `linux/gpio/consumer.h`, `linux/iio/iio.h`, `linux/limits.h`, `linux/module.h`, `linux/regulator/consumer.h`, `linux/slab.h`, `linux/spi/spi.h`.
- Detected declarations: `struct x9250_cfg`, `struct x9250`, `enum x9250_type`, `function x9250_write8`, `function x9250_read8`, `function x9250_read_raw`, `function x9250_read_avail`, `function x9250_write_raw`, `function x9250_probe`.
- Atlas domain: Driver Families / drivers/iio.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.