drivers/infiniband/hw/hfi1/chip_registers.h

Source file repositories/reference/linux-study-clean/drivers/infiniband/hw/hfi1/chip_registers.h

File Facts

System: Linux kernel
Corpus path: drivers/infiniband/hw/hfi1/chip_registers.h
Extension: .h
Size: 67428 bytes
Lines: 1296
Domain: Driver Families
Bucket: drivers/infiniband
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef DEF_CHIP_REG
#define DEF_CHIP_REG

#define CORE		0x000000000000
#define CCE			(CORE + 0x000000000000)
#define ASIC		(CORE + 0x000000400000)
#define MISC		(CORE + 0x000000500000)
#define DC_TOP_CSRS		(CORE + 0x000000600000)
#define CHIP_DEBUG		(CORE + 0x000000700000)
#define RXE			(CORE + 0x000001000000)
#define TXE			(CORE + 0x000001800000)
#define DCC_CSRS		(DC_TOP_CSRS + 0x000000000000)
#define DC_LCB_CSRS		(DC_TOP_CSRS + 0x000000001000)
#define DC_8051_CSRS		(DC_TOP_CSRS + 0x000000002000)
#define PCIE		0

#define ASIC_NUM_SCRATCH 4
#define CCE_ERR_INT_CNT 0
#define CCE_MISC_INT_CNT 2
#define CCE_NUM_32_BIT_COUNTERS 3
#define CCE_NUM_32_BIT_INT_COUNTERS 6
#define CCE_NUM_INT_CSRS 12
#define CCE_NUM_INT_MAP_CSRS 96
#define CCE_NUM_MSIX_PBAS 4
#define CCE_NUM_MSIX_VECTORS 256
#define CCE_NUM_SCRATCH 4
#define CCE_PCIE_POSTED_CRDT_STALL_CNT 2
#define CCE_PCIE_TRGT_STALL_CNT 0
#define CCE_PIO_WR_STALL_CNT 1
#define CCE_RCV_AVAIL_INT_CNT 3
#define CCE_RCV_URGENT_INT_CNT 4
#define CCE_SDMA_INT_CNT 1
#define CCE_SEND_CREDIT_INT_CNT 5
#define DCC_CFG_LED_CNTRL (DCC_CSRS + 0x000000000040)
#define DCC_CFG_LED_CNTRL_LED_CNTRL_SMASK 0x10ull
#define DCC_CFG_LED_CNTRL_LED_SW_BLINK_RATE_SHIFT 0
#define DCC_CFG_LED_CNTRL_LED_SW_BLINK_RATE_SMASK 0xFull
#define DCC_CFG_PORT_CONFIG (DCC_CSRS + 0x000000000008)
#define DCC_CFG_PORT_CONFIG1 (DCC_CSRS + 0x000000000010)
#define DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK 0xFFFFull
#define DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT 16
#define DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK 0xFFFF0000ull
#define DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK 0xFFFFull
#define DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT 0
#define DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK 0xFFFFull
#define DCC_CFG_PORT_CONFIG_LINK_STATE_MASK 0x7ull
#define DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT 48
#define DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK 0x7000000000000ull
#define DCC_CFG_PORT_CONFIG_MTU_CAP_MASK 0x7ull
#define DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT 32
#define DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK 0x700000000ull
#define DCC_CFG_RESET (DCC_CSRS + 0x000000000000)
#define DCC_CFG_RESET_RESET_LCB          BIT_ULL(0)
#define DCC_CFG_RESET_RESET_TX_FPE       BIT_ULL(1)
#define DCC_CFG_RESET_RESET_RX_FPE       BIT_ULL(2)
#define DCC_CFG_RESET_RESET_8051         BIT_ULL(3)
#define DCC_CFG_RESET_ENABLE_CCLK_BCC    BIT_ULL(4)
#define DCC_CFG_SC_VL_TABLE_15_0 (DCC_CSRS + 0x000000000028)
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY0_SHIFT 0
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY10_SHIFT 40
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY11_SHIFT 44
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY12_SHIFT 48
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY13_SHIFT 52
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY14_SHIFT 56
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY15_SHIFT 60
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY1_SHIFT 4
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY2_SHIFT 8
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY3_SHIFT 12
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY4_SHIFT 16
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY5_SHIFT 20
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY6_SHIFT 24
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY7_SHIFT 28
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY8_SHIFT 32
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY9_SHIFT 36
#define DCC_CFG_SC_VL_TABLE_31_16 (DCC_CSRS + 0x000000000030)
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY16_SHIFT 0
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY17_SHIFT 4
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY18_SHIFT 8
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY19_SHIFT 12
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY20_SHIFT 16
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY21_SHIFT 20
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY22_SHIFT 24
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY23_SHIFT 28
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY24_SHIFT 32
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY25_SHIFT 36
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY26_SHIFT 40
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY27_SHIFT 44
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY28_SHIFT 48
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY29_SHIFT 52
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY30_SHIFT 56

Annotation

Atlas domain: Driver Families / drivers/infiniband.
Implementation status: source implementation candidate.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.