drivers/infiniband/hw/hfi1/sdma.c
Source file repositories/reference/linux-study-clean/drivers/infiniband/hw/hfi1/sdma.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/infiniband/hw/hfi1/sdma.c- Extension
.c- Size
- 89721 bytes
- Lines
- 3367
- Domain
- Driver Families
- Bucket
- drivers/infiniband
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/spinlock.hlinux/seqlock.hlinux/netdevice.hlinux/moduleparam.hlinux/bitops.hlinux/timer.hlinux/vmalloc.hlinux/highmem.hhfi.hcommon.hqp.hsdma.hiowait.htrace.h
Detected Declarations
struct sdma_rht_map_elemstruct sdma_rht_nodefunction sdma_state_namefunction sdma_getfunction sdma_completefunction sdma_putfunction sdma_finalputfunction write_sde_csrfunction read_sde_csrfunction sdma_wait_for_packet_egressfunction sdma_waitfunction sdma_set_desc_cntfunction complete_txfunction sdma_flushfunction list_for_each_entry_safefunction sdma_field_flushfunction sdma_err_halt_waitfunction sdma_err_progress_check_schedulefunction sdma_err_progress_checkfunction sdma_hw_clean_up_taskfunction sdma_flush_descqfunction sdma_sw_clean_up_taskfunction sdma_sw_tear_downfunction sdma_start_hw_clean_upfunction sdma_set_statefunction sdma_get_descq_cntfunction sdma_engine_get_vlfunction sdma_select_engine_vlfunction sdma_select_engine_scfunction sdma_select_user_enginefunction sdma_populate_sde_mapfunction sdma_cleanup_sde_mapfunction sdma_set_cpu_to_sde_mapfunction for_each_cpufunction sdma_get_cpu_to_sde_mapfunction sdma_rht_freefunction sdma_seqfile_dump_cpu_listfunction sdma_map_freefunction sdma_map_rcu_callbackfunction sdma_map_initfunction sdma_initfunction sdma_initfunction sdma_all_runningfunction sdma_startfunction sdma_exitfunction sdma_unmap_descfunction ahg_modefunction __sdma_txclean
Annotated Snippet
struct sdma_rht_map_elem {
u32 mask;
u8 ctr;
struct sdma_engine *sde[];
};
struct sdma_rht_node {
unsigned long cpu_id;
struct sdma_rht_map_elem *map[HFI1_MAX_VLS_SUPPORTED];
struct rhash_head node;
};
#define NR_CPUS_HINT 192
static const struct rhashtable_params sdma_rht_params = {
.nelem_hint = NR_CPUS_HINT,
.head_offset = offsetof(struct sdma_rht_node, node),
.key_offset = offsetof(struct sdma_rht_node, cpu_id),
.key_len = sizeof_field(struct sdma_rht_node, cpu_id),
.max_size = NR_CPUS,
.min_size = 8,
.automatic_shrinking = true,
};
/*
* sdma_select_user_engine() - select sdma engine based on user setup
* @dd: devdata
* @selector: a spreading factor
* @vl: this vl
*
* This function returns an sdma engine for a user sdma request.
* User defined sdma engine affinity setting is honored when applicable,
* otherwise system default sdma engine mapping is used. To ensure correct
* ordering, the mapping from <selector, vl> to sde must remain unchanged.
*/
struct sdma_engine *sdma_select_user_engine(struct hfi1_devdata *dd,
u32 selector, u8 vl)
{
struct sdma_rht_node *rht_node;
struct sdma_engine *sde = NULL;
unsigned long cpu_id;
/*
* To ensure that always the same sdma engine(s) will be
* selected make sure the process is pinned to this CPU only.
*/
if (current->nr_cpus_allowed != 1)
goto out;
rcu_read_lock();
cpu_id = smp_processor_id();
rht_node = rhashtable_lookup(dd->sdma_rht, &cpu_id,
sdma_rht_params);
if (rht_node && rht_node->map[vl]) {
struct sdma_rht_map_elem *map = rht_node->map[vl];
sde = map->sde[selector & map->mask];
}
rcu_read_unlock();
if (sde)
return sde;
out:
return sdma_select_engine_vl(dd, selector, vl);
}
static void sdma_populate_sde_map(struct sdma_rht_map_elem *map)
{
int i;
for (i = 0; i < roundup_pow_of_two(map->ctr ? : 1) - map->ctr; i++)
map->sde[map->ctr + i] = map->sde[i];
}
static void sdma_cleanup_sde_map(struct sdma_rht_map_elem *map,
struct sdma_engine *sde)
{
unsigned int i, pow;
/* only need to check the first ctr entries for a match */
for (i = 0; i < map->ctr; i++) {
if (map->sde[i] == sde) {
memmove(&map->sde[i], &map->sde[i + 1],
(map->ctr - i - 1) * sizeof(map->sde[0]));
map->ctr--;
pow = roundup_pow_of_two(map->ctr ? : 1);
map->mask = pow - 1;
sdma_populate_sde_map(map);
Annotation
- Immediate include surface: `linux/spinlock.h`, `linux/seqlock.h`, `linux/netdevice.h`, `linux/moduleparam.h`, `linux/bitops.h`, `linux/timer.h`, `linux/vmalloc.h`, `linux/highmem.h`.
- Detected declarations: `struct sdma_rht_map_elem`, `struct sdma_rht_node`, `function sdma_state_name`, `function sdma_get`, `function sdma_complete`, `function sdma_put`, `function sdma_finalput`, `function write_sde_csr`, `function read_sde_csr`, `function sdma_wait_for_packet_egress`.
- Atlas domain: Driver Families / drivers/infiniband.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.