drivers/infiniband/hw/irdma/uda.c

Source file repositories/reference/linux-study-clean/drivers/infiniband/hw/irdma/uda.c

File Facts

System
Linux kernel
Corpus path
drivers/infiniband/hw/irdma/uda.c
Extension
.c
Size
8191 bytes
Lines
266
Domain
Driver Families
Bucket
drivers/infiniband
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (entry_info->valid_entry) {
			set_64bit_val((__le64 *)info->dma_mem_mc.va,
				      ctx_idx * sizeof(u64),
				      FIELD_PREP(IRDMA_UDA_MGCTX_DESTPORT, entry_info->dest_port) |
				      FIELD_PREP(IRDMA_UDA_MGCTX_VALIDENT, entry_info->valid_entry) |
				      FIELD_PREP(IRDMA_UDA_MGCTX_QPID, entry_info->qp_id));
			ctx_idx++;
		}
	}
}

/**
 * irdma_access_mcast_grp() - Access mcast group based on op
 * @cqp: Control QP
 * @info: multicast group context info
 * @op: operation to perform
 * @scratch: u64 saved to be used during cqp completion
 */
int irdma_access_mcast_grp(struct irdma_sc_cqp *cqp,
			   struct irdma_mcast_grp_info *info, u32 op,
			   u64 scratch)
{
	__le64 *wqe;

	if (info->mg_id >= IRDMA_UDA_MAX_FSI_MGS) {
		ibdev_dbg(to_ibdev(cqp->dev), "WQE: mg_id out of range\n");
		return -EINVAL;
	}

	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
	if (!wqe) {
		ibdev_dbg(to_ibdev(cqp->dev), "WQE: ring full\n");
		return -ENOMEM;
	}

	irdma_create_mg_ctx(info);

	set_64bit_val(wqe, 32, info->dma_mem_mc.pa);
	set_64bit_val(wqe, 16,
		      FIELD_PREP(IRDMA_UDA_CQPSQ_MG_VLANID, info->vlan_id) |
		      FIELD_PREP(IRDMA_UDA_CQPSQ_QS_HANDLE, info->qs_handle));
	set_64bit_val(wqe, 0, ether_addr_to_u64(info->dest_mac_addr));
	set_64bit_val(wqe, 8,
		      FIELD_PREP(IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID, info->hmc_fcn_id));

	if (!info->ipv4_valid) {
		set_64bit_val(wqe, 56,
			      FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR0, info->dest_ip_addr[0]) |
			      FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR1, info->dest_ip_addr[1]));
		set_64bit_val(wqe, 48,
			      FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR2, info->dest_ip_addr[2]) |
			      FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR3, info->dest_ip_addr[3]));
	} else {
		set_64bit_val(wqe, 48,
			      FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR3, info->dest_ip_addr[0]));
	}

	dma_wmb(); /* need write memory block before writing the WQE header. */

	set_64bit_val(wqe, 24,
		      FIELD_PREP(IRDMA_UDA_CQPSQ_MG_WQEVALID, cqp->polarity) |
		      FIELD_PREP(IRDMA_UDA_CQPSQ_MG_OPCODE, op) |
		      FIELD_PREP(IRDMA_UDA_CQPSQ_MG_MGIDX, info->mg_id) |
		      FIELD_PREP(IRDMA_UDA_CQPSQ_MG_VLANVALID, info->vlan_valid) |
		      FIELD_PREP(IRDMA_UDA_CQPSQ_MG_IPV4VALID, info->ipv4_valid));

	print_hex_dump_debug("WQE: MANAGE_MCG WQE", DUMP_PREFIX_OFFSET, 16, 8,
			     wqe, IRDMA_CQP_WQE_SIZE * 8, false);
	print_hex_dump_debug("WQE: MCG_HOST CTX WQE", DUMP_PREFIX_OFFSET, 16,
			     8, info->dma_mem_mc.va,
			     IRDMA_MAX_MGS_PER_CTX * 8, false);
	irdma_sc_cqp_post_sq(cqp);

	return 0;
}

/**
 * irdma_compare_mgs - Compares two multicast group structures
 * @entry1: Multcast group info
 * @entry2: Multcast group info in context
 */
static bool irdma_compare_mgs(struct irdma_mcast_grp_ctx_entry_info *entry1,
			      struct irdma_mcast_grp_ctx_entry_info *entry2)
{
	if (entry1->dest_port == entry2->dest_port &&
	    entry1->qp_id == entry2->qp_id)
		return true;

	return false;
}

Annotation

Implementation Notes