drivers/input/serio/olpc_apsp.c
Source file repositories/reference/linux-study-clean/drivers/input/serio/olpc_apsp.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/input/serio/olpc_apsp.c- Extension
.c- Size
- 6996 bytes
- Lines
- 269
- Domain
- Driver Families
- Bucket
- drivers/input
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hlinux/interrupt.hlinux/serio.hlinux/err.hlinux/platform_device.hlinux/io.hlinux/of.hlinux/slab.hlinux/delay.h
Detected Declarations
struct olpc_apspfunction olpc_apsp_writefunction olpc_apsp_rxfunction olpc_apsp_openfunction olpc_apsp_closefunction olpc_apsp_probefunction olpc_apsp_remove
Annotated Snippet
struct olpc_apsp {
struct device *dev;
struct serio *kbio;
struct serio *padio;
void __iomem *base;
int open_count;
int irq;
};
static int olpc_apsp_write(struct serio *port, unsigned char val)
{
struct olpc_apsp *priv = port->port_data;
unsigned int i;
u32 which = 0;
if (port == priv->padio)
which = TOUCHPAD_PORT << PORT_SHIFT;
else
which = KEYBOARD_PORT << PORT_SHIFT;
dev_dbg(priv->dev, "olpc_apsp_write which=%x val=%x\n", which, val);
for (i = 0; i < 50; i++) {
u32 sts = readl(priv->base + COMMAND_FIFO_STATUS);
if ((sts & CMD_CNTR_MASK) < MAX_PENDING_CMDS) {
writel(which | val,
priv->base + SECURE_PROCESSOR_COMMAND);
return 0;
}
/* SP busy. This has not been seen in practice. */
mdelay(1);
}
dev_dbg(priv->dev, "olpc_apsp_write timeout, status=%x\n",
readl(priv->base + COMMAND_FIFO_STATUS));
return -ETIMEDOUT;
}
static irqreturn_t olpc_apsp_rx(int irq, void *dev_id)
{
struct olpc_apsp *priv = dev_id;
unsigned int w, tmp;
struct serio *serio;
/*
* Write 1 to PJ_RST_INTERRUPT to acknowledge and clear the interrupt
* Write 0xff00 to SECURE_PROCESSOR_COMMAND.
*/
tmp = readl(priv->base + PJ_RST_INTERRUPT);
if (!(tmp & SP_COMMAND_COMPLETE_RESET)) {
dev_warn(priv->dev, "spurious interrupt?\n");
return IRQ_NONE;
}
w = readl(priv->base + COMMAND_RETURN_STATUS);
dev_dbg(priv->dev, "olpc_apsp_rx %x\n", w);
if (w >> PORT_SHIFT == KEYBOARD_PORT)
serio = priv->kbio;
else
serio = priv->padio;
serio_interrupt(serio, w & DATA_MASK, 0);
/* Ack and clear interrupt */
writel(tmp | SP_COMMAND_COMPLETE_RESET, priv->base + PJ_RST_INTERRUPT);
writel(PORT_MASK, priv->base + SECURE_PROCESSOR_COMMAND);
pm_wakeup_event(priv->dev, 1000);
return IRQ_HANDLED;
}
static int olpc_apsp_open(struct serio *port)
{
struct olpc_apsp *priv = port->port_data;
unsigned int tmp;
unsigned long l;
if (priv->open_count++ == 0) {
l = readl(priv->base + COMMAND_FIFO_STATUS);
if (!(l & CMD_STS_MASK)) {
dev_err(priv->dev, "SP cannot accept commands.\n");
return -EIO;
}
/* Enable interrupt 0 by clearing its bit */
tmp = readl(priv->base + PJ_INTERRUPT_MASK);
writel(tmp & ~INT_0, priv->base + PJ_INTERRUPT_MASK);
}
Annotation
- Immediate include surface: `linux/module.h`, `linux/interrupt.h`, `linux/serio.h`, `linux/err.h`, `linux/platform_device.h`, `linux/io.h`, `linux/of.h`, `linux/slab.h`.
- Detected declarations: `struct olpc_apsp`, `function olpc_apsp_write`, `function olpc_apsp_rx`, `function olpc_apsp_open`, `function olpc_apsp_close`, `function olpc_apsp_probe`, `function olpc_apsp_remove`.
- Atlas domain: Driver Families / drivers/input.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.