drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c

Source file repositories/reference/linux-study-clean/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c

File Facts

System
Linux kernel
Corpus path
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
Extension
.c
Size
27098 bytes
Lines
850
Domain
Driver Families
Bucket
drivers/iommu
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

of_device_is_compatible(np, "qcom,adreno-smmu")) {
		priv->set_prr_bit = qcom_adreno_smmu_set_prr_bit;
		priv->set_prr_addr = qcom_adreno_smmu_set_prr_addr;
	}

	return 0;
}

static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
	{ .compatible = "qcom,adreno" },
	{ .compatible = "qcom,adreno-gmu" },
	{ .compatible = "qcom,glymur-mdss" },
	{ .compatible = "qcom,mdp4" },
	{ .compatible = "qcom,mdss" },
	{ .compatible = "qcom,qcm2290-mdss" },
	{ .compatible = "qcom,sar2130p-mdss" },
	{ .compatible = "qcom,sc7180-mdss" },
	{ .compatible = "qcom,sc7180-mss-pil" },
	{ .compatible = "qcom,sc7280-mdss" },
	{ .compatible = "qcom,sc7280-mss-pil" },
	{ .compatible = "qcom,sc8180x-mdss" },
	{ .compatible = "qcom,sc8280xp-mdss" },
	{ .compatible = "qcom,sdm670-mdss" },
	{ .compatible = "qcom,sdm845-mdss" },
	{ .compatible = "qcom,sdm845-mss-pil" },
	{ .compatible = "qcom,sm6115-mdss" },
	{ .compatible = "qcom,sm6350-mdss" },
	{ .compatible = "qcom,sm6375-mdss" },
	{ .compatible = "qcom,sm8150-mdss" },
	{ .compatible = "qcom,sm8250-mdss" },
	{ .compatible = "qcom,x1e80100-mdss" },
	{ }
};

static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
{
	struct arm_smmu_device *smmu = smmu_domain->smmu;
	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
	const struct of_device_id *client_match;
	int cbndx = smmu_domain->cfg.cbndx;

	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;

	client_match = qsmmu->data->client_match;

	if (client_match)
		qcom_smmu_set_actlr_dev(dev, smmu, cbndx, client_match);

	return 0;
}

static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
{
	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
	unsigned int last_s2cr;
	u32 reg;
	u32 smr;
	int i;

	/*
	 * MSM8998 LPASS SMMU reports 13 context banks, but accessing
	 * the last context bank crashes the system.
	 */
	if (of_device_is_compatible(smmu->dev->of_node, "qcom,msm8998-smmu-v2") &&
	    smmu->num_context_banks == 13) {
		smmu->num_context_banks = 12;
	} else if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2")) {
		if (smmu->num_context_banks == 21) /* SDM630 / SDM660 A2NOC SMMU */
			smmu->num_context_banks = 7;
		else if (smmu->num_context_banks == 14) /* SDM630 / SDM660 LPASS SMMU */
			smmu->num_context_banks = 13;
	}

	/*
	 * Some platforms support more than the Arm SMMU architected maximum of
	 * 128 stream matching groups. The additional registers appear to have
	 * the same behavior as the architected registers in the hardware.
	 * However, on some firmware versions, the hypervisor does not
	 * correctly trap and emulate accesses to the additional registers,
	 * resulting in unexpected behavior.
	 *
	 * If there are more than 128 groups, use the last reliable group to
	 * detect if we need to apply the bypass quirk.
	 */
	if (smmu->num_mapping_groups > 128)
		last_s2cr = ARM_SMMU_GR0_S2CR(127);
	else
		last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);

Annotation

Implementation Notes