drivers/iommu/fsl_pamu.h

Source file repositories/reference/linux-study-clean/drivers/iommu/fsl_pamu.h

File Facts

System
Linux kernel
Corpus path
drivers/iommu/fsl_pamu.h
Extension
.h
Size
12551 bytes
Lines
393
Domain
Driver Families
Bucket
drivers/iommu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct pamu_mmap_regs {
	u32 ppbah;
	u32 ppbal;
	u32 pplah;
	u32 pplal;
	u32 spbah;
	u32 spbal;
	u32 splah;
	u32 splal;
	u32 obah;
	u32 obal;
	u32 olah;
	u32 olal;
};

/* PAMU Error Registers */
#define PAMU_POES1 0x0040
#define PAMU_POES2 0x0044
#define PAMU_POEAH 0x0048
#define PAMU_POEAL 0x004C
#define PAMU_AVS1  0x0050
#define PAMU_AVS1_AV    0x1
#define PAMU_AVS1_OTV   0x6
#define PAMU_AVS1_APV   0x78
#define PAMU_AVS1_WAV   0x380
#define PAMU_AVS1_LAV   0x1c00
#define PAMU_AVS1_GCV   0x2000
#define PAMU_AVS1_PDV   0x4000
#define PAMU_AV_MASK    (PAMU_AVS1_AV | PAMU_AVS1_OTV | PAMU_AVS1_APV | PAMU_AVS1_WAV \
			 | PAMU_AVS1_LAV | PAMU_AVS1_GCV | PAMU_AVS1_PDV)
#define PAMU_AVS1_LIODN_SHIFT 16
#define PAMU_LAV_LIODN_NOT_IN_PPAACT 0x400

#define PAMU_AVS2  0x0054
#define PAMU_AVAH  0x0058
#define PAMU_AVAL  0x005C
#define PAMU_EECTL 0x0060
#define PAMU_EEDIS 0x0064
#define PAMU_EEINTEN 0x0068
#define PAMU_EEDET 0x006C
#define PAMU_EEATTR 0x0070
#define PAMU_EEAHI 0x0074
#define PAMU_EEALO 0x0078
#define PAMU_EEDHI 0X007C
#define PAMU_EEDLO 0x0080
#define PAMU_EECC  0x0084
#define PAMU_UDAD  0x0090

/* PAMU Revision Registers */
#define PAMU_PR1 0x0BF8
#define PAMU_PR2 0x0BFC

/* PAMU version mask */
#define PAMU_PR1_MASK 0xffff

/* PAMU Capabilities Registers */
#define PAMU_PC1 0x0C00
#define PAMU_PC2 0x0C04
#define PAMU_PC3 0x0C08
#define PAMU_PC4 0x0C0C

/* PAMU Control Register */
#define PAMU_PC 0x0C10

/* PAMU control defs */
#define PAMU_CONTROL 0x0C10
#define PAMU_PC_PGC 0x80000000  /* PAMU gate closed bit */
#define PAMU_PC_PE   0x40000000 /* PAMU enable bit */
#define PAMU_PC_SPCC 0x00000010 /* sPAACE cache enable */
#define PAMU_PC_PPCC 0x00000001 /* pPAACE cache enable */
#define PAMU_PC_OCE  0x00001000 /* OMT cache enable */

#define PAMU_PFA1 0x0C14
#define PAMU_PFA2 0x0C18

#define PAMU_PC2_MLIODN(X) ((X) >> 16)
#define PAMU_PC3_MWCE(X) (((X) >> 21) & 0xf)

/* PAMU Interrupt control and Status Register */
#define PAMU_PICS 0x0C1C
#define PAMU_ACCESS_VIOLATION_STAT   0x8
#define PAMU_ACCESS_VIOLATION_ENABLE 0x4

/* PAMU Debug Registers */
#define PAMU_PD1 0x0F00
#define PAMU_PD2 0x0F04
#define PAMU_PD3 0x0F08
#define PAMU_PD4 0x0F0C

#define PAACE_AP_PERMS_DENIED  0x0

Annotation

Implementation Notes