drivers/iommu/intel/iommu.c
Source file repositories/reference/linux-study-clean/drivers/iommu/intel/iommu.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/iommu/intel/iommu.c- Extension
.c- Size
- 112328 bytes
- Lines
- 4232
- Domain
- Driver Families
- Bucket
- drivers/iommu
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/crash_dump.hlinux/dma-direct.hlinux/dmi.hlinux/memory.hlinux/pci.hlinux/pci-ats.hlinux/spinlock.hlinux/syscore_ops.hlinux/tboot.huapi/linux/iommufd.hiommu.h../dma-iommu.h../irq_remapping.h../iommu-pages.hpasid.hperfmon.h
Detected Declarations
struct dmar_rmrr_unitstruct dmar_atsr_unitstruct dmar_satc_unitfunction Pointerfunction Pointerfunction device_rid_cmp_keyfunction device_rid_cmpfunction device_rbtree_insertfunction device_rbtree_removefunction translation_pre_enabledfunction clear_translation_pre_enabledfunction init_translation_statusfunction intel_iommu_setupfunction __iommu_calculate_sagawfunction __iommu_calculate_agawfunction iommu_calculate_max_sagawfunction iommu_calculate_agawfunction iommu_paging_structure_coherencyfunction is_downstream_to_pci_bridgefunction quirk_ioat_snb_local_iommufunction iommu_is_dummyfunction for_each_active_dev_scopefunction free_context_tablefunction pgtable_walkfunction dmar_fault_dump_ptesfunction iommu_alloc_root_entryfunction iommu_set_root_entryfunction iommu_flush_write_bufferfunction __iommu_flush_contextfunction __iommu_flush_iotlbfunction domain_lookup_dev_infofunction dev_needs_extra_dtlb_flushfunction iommu_enable_pci_atsfunction iommu_disable_pci_atsfunction iommu_enable_pci_prifunction iommu_disable_pci_prifunction intel_flush_iotlb_allfunction iommu_disable_protect_mem_regionsfunction iommu_enable_translationfunction iommu_disable_translationfunction disable_dmar_iommufunction free_dmar_iommufunction first_level_by_defaultfunction domain_attach_iommufunction domain_detach_iommufunction copied_context_tear_downfunction context_present_cache_flushfunction domain_context_mapping_one
Annotated Snippet
struct dmar_rmrr_unit {
struct list_head list; /* list of rmrr units */
struct acpi_dmar_header *hdr; /* ACPI header */
u64 base_address; /* reserved base address*/
u64 end_address; /* reserved end address */
struct dmar_dev_scope *devices; /* target devices */
int devices_cnt; /* target device count */
};
struct dmar_atsr_unit {
struct list_head list; /* list of ATSR units */
struct acpi_dmar_header *hdr; /* ACPI header */
struct dmar_dev_scope *devices; /* target devices */
int devices_cnt; /* target device count */
u8 include_all:1; /* include all ports */
};
struct dmar_satc_unit {
struct list_head list; /* list of SATC units */
struct acpi_dmar_header *hdr; /* ACPI header */
struct dmar_dev_scope *devices; /* target devices */
struct intel_iommu *iommu; /* the corresponding iommu */
int devices_cnt; /* target device count */
u8 atc_required:1; /* ATS is required */
};
static LIST_HEAD(dmar_atsr_units);
static LIST_HEAD(dmar_rmrr_units);
static LIST_HEAD(dmar_satc_units);
#define for_each_rmrr_units(rmrr) \
list_for_each_entry(rmrr, &dmar_rmrr_units, list)
static void intel_iommu_domain_free(struct iommu_domain *domain);
int dmar_disabled = !IS_ENABLED(CONFIG_INTEL_IOMMU_DEFAULT_ON);
int intel_iommu_sm = IS_ENABLED(CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON);
int intel_iommu_enabled = 0;
EXPORT_SYMBOL_GPL(intel_iommu_enabled);
static int intel_iommu_superpage = 1;
static int iommu_identity_mapping;
static int iommu_skip_te_disable;
static int disable_igfx_iommu;
#define IDENTMAP_AZALIA 4
const struct iommu_ops intel_iommu_ops;
static bool translation_pre_enabled(struct intel_iommu *iommu)
{
return (iommu->flags & VTD_FLAG_TRANS_PRE_ENABLED);
}
static void clear_translation_pre_enabled(struct intel_iommu *iommu)
{
iommu->flags &= ~VTD_FLAG_TRANS_PRE_ENABLED;
}
static void init_translation_status(struct intel_iommu *iommu)
{
u32 gsts;
gsts = readl(iommu->reg + DMAR_GSTS_REG);
if (gsts & DMA_GSTS_TES)
iommu->flags |= VTD_FLAG_TRANS_PRE_ENABLED;
}
static int __init intel_iommu_setup(char *str)
{
if (!str)
return -EINVAL;
while (*str) {
if (!strncmp(str, "on", 2)) {
dmar_disabled = 0;
pr_info("IOMMU enabled\n");
} else if (!strncmp(str, "off", 3)) {
dmar_disabled = 1;
no_platform_optin = 1;
pr_info("IOMMU disabled\n");
} else if (!strncmp(str, "igfx_off", 8)) {
disable_igfx_iommu = 1;
pr_info("Disable GFX device mapping\n");
} else if (!strncmp(str, "forcedac", 8)) {
pr_warn("intel_iommu=forcedac deprecated; use iommu.forcedac instead\n");
iommu_dma_forcedac = true;
} else if (!strncmp(str, "strict", 6)) {
pr_warn("intel_iommu=strict deprecated; use iommu.strict=1 instead\n");
Annotation
- Immediate include surface: `linux/crash_dump.h`, `linux/dma-direct.h`, `linux/dmi.h`, `linux/memory.h`, `linux/pci.h`, `linux/pci-ats.h`, `linux/spinlock.h`, `linux/syscore_ops.h`.
- Detected declarations: `struct dmar_rmrr_unit`, `struct dmar_atsr_unit`, `struct dmar_satc_unit`, `function Pointer`, `function Pointer`, `function device_rid_cmp_key`, `function device_rid_cmp`, `function device_rbtree_insert`, `function device_rbtree_remove`, `function translation_pre_enabled`.
- Atlas domain: Driver Families / drivers/iommu.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.