drivers/iommu/intel/irq_remapping.c
Source file repositories/reference/linux-study-clean/drivers/iommu/intel/irq_remapping.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/iommu/intel/irq_remapping.c- Extension
.c- Size
- 40938 bytes
- Lines
- 1606
- Domain
- Driver Families
- Bucket
- drivers/iommu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/interrupt.hlinux/dmar.hlinux/spinlock.hlinux/slab.hlinux/jiffies.hlinux/hpet.hlinux/pci.hlinux/irq.hlinux/irqchip/irq-msi-lib.hlinux/acpi.hlinux/irqdomain.hlinux/crash_dump.hasm/io_apic.hasm/apic.hasm/smp.hasm/cpu.hasm/irq_remapping.hasm/pci-direct.hasm/posted_intr.hiommu.h../irq_remapping.h../iommu-pages.h
Detected Declarations
struct ioapic_scopestruct hpet_scopestruct irq_2_iommustruct intel_ir_datastruct set_msi_sid_datafunction ir_pre_enabledfunction clear_ir_pre_enabledfunction init_ir_statusfunction alloc_irtefunction qi_flush_iecfunction modify_irtefunction clear_entriesfunction set_irte_sidfunction set_irte_verify_busfunction set_ioapic_sidfunction set_hpet_sidfunction set_msi_sid_cbfunction set_msi_sidfunction iommu_load_old_irtefunction iommu_set_irq_remappingfunction iommu_enable_irq_remappingfunction intel_setup_irq_remappingfunction intel_teardown_irq_remappingfunction iommu_disable_irq_remappingfunction dmar_x2apic_optoutfunction intel_cleanup_irq_remappingfunction for_each_iommufunction intel_prepare_irq_remappingfunction for_each_iommufunction set_irq_posting_capfunction for_each_iommufunction intel_enable_irq_remappingfunction ir_parse_one_hpet_scopefunction ir_parse_one_ioapic_scopefunction ir_parse_ioapic_hpet_scopefunction ir_remove_ioapic_hpet_scopefunction parse_ioapics_under_irfunction for_each_iommufunction ir_dev_scope_initfunction disable_irq_remappingfunction reenable_irq_remappingfunction dmar_pci_bus_add_devfunction prepare_irtefunction prepare_irte_postedfunction get_pi_desc_addrfunction intel_ir_reconfigure_irte_postedfunction intel_ir_reconfigure_irte_postedfunction intel_ir_reconfigure_irte
Annotated Snippet
struct ioapic_scope {
struct intel_iommu *iommu;
unsigned int id;
unsigned int bus; /* PCI bus number */
unsigned int devfn; /* PCI devfn number */
};
struct hpet_scope {
struct intel_iommu *iommu;
u8 id;
unsigned int bus;
unsigned int devfn;
};
struct irq_2_iommu {
struct intel_iommu *iommu;
u16 irte_index;
u16 sub_handle;
u8 irte_mask;
bool posted_msi;
bool posted_vcpu;
};
struct intel_ir_data {
struct irq_2_iommu irq_2_iommu;
struct irte irte_entry;
union {
struct msi_msg msi_entry;
};
};
#define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
#define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
static int __read_mostly eim_mode;
static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
static struct hpet_scope ir_hpet[MAX_HPET_TBS];
/*
* Lock ordering:
* ->dmar_global_lock
* ->irq_2_ir_lock
* ->qi->q_lock
* ->iommu->register_lock
* Note:
* intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
* in single-threaded environment with interrupt disabled, so no need to tabke
* the dmar_global_lock.
*/
DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
static const struct irq_domain_ops intel_ir_domain_ops;
static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
static int __init parse_ioapics_under_ir(void);
static const struct msi_parent_ops dmar_msi_parent_ops;
static bool ir_pre_enabled(struct intel_iommu *iommu)
{
return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
}
static void clear_ir_pre_enabled(struct intel_iommu *iommu)
{
iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
}
static void init_ir_status(struct intel_iommu *iommu)
{
u32 gsts;
gsts = readl(iommu->reg + DMAR_GSTS_REG);
if (gsts & DMA_GSTS_IRES)
iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
}
static int alloc_irte(struct intel_iommu *iommu,
struct irq_2_iommu *irq_iommu, u16 count)
{
struct ir_table *table = iommu->ir_table;
unsigned int mask = 0;
unsigned long flags;
int index;
if (!count || !irq_iommu)
return -1;
if (count > 1) {
count = __roundup_pow_of_two(count);
mask = ilog2(count);
}
Annotation
- Immediate include surface: `linux/interrupt.h`, `linux/dmar.h`, `linux/spinlock.h`, `linux/slab.h`, `linux/jiffies.h`, `linux/hpet.h`, `linux/pci.h`, `linux/irq.h`.
- Detected declarations: `struct ioapic_scope`, `struct hpet_scope`, `struct irq_2_iommu`, `struct intel_ir_data`, `struct set_msi_sid_data`, `function ir_pre_enabled`, `function clear_ir_pre_enabled`, `function init_ir_status`, `function alloc_irte`, `function qi_flush_iec`.
- Atlas domain: Driver Families / drivers/iommu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.