drivers/iommu/msm_iommu_hw-8xxx.h

Source file repositories/reference/linux-study-clean/drivers/iommu/msm_iommu_hw-8xxx.h

File Facts

System
Linux kernel
Corpus path
drivers/iommu/msm_iommu_hw-8xxx.h
Extension
.h
Size
75136 bytes
Lines
1853
Domain
Driver Families
Bucket
drivers/iommu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
#define __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H

#define CTX_SHIFT 12

#define GET_GLOBAL_REG(reg, base) (readl((base) + (reg)))
#define GET_CTX_REG(reg, base, ctx) \
				(readl((base) + (reg) + ((ctx) << CTX_SHIFT)))

#define SET_GLOBAL_REG(reg, base, val)	writel((val), ((base) + (reg)))

#define SET_CTX_REG(reg, base, ctx, val) \
			writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT)))

/* Wrappers for numbered registers */
#define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v))
#define GET_GLOBAL_REG_N(b, n, r)    GET_GLOBAL_REG(b, ((r) + (n << 2)))

/* Field wrappers */
#define GET_GLOBAL_FIELD(b, r, F)    GET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT)
#define GET_CONTEXT_FIELD(b, c, r, F)	\
	GET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT)

#define SET_GLOBAL_FIELD(b, r, F, v) \
	SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
#define SET_CONTEXT_FIELD(b, c, r, F, v)	\
	SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))

#define GET_FIELD(addr, mask, shift)  ((readl(addr) >> (shift)) & (mask))

#define SET_FIELD(addr, mask, shift, v) \
do { \
	int t = readl(addr); \
	writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\
} while (0)


#define NUM_FL_PTE	4096
#define NUM_SL_PTE	256
#define NUM_TEX_CLASS	8

/* First-level page table bits */
#define FL_BASE_MASK		0xFFFFFC00
#define FL_TYPE_TABLE		(1 << 0)
#define FL_TYPE_SECT		(2 << 0)
#define FL_SUPERSECTION		(1 << 18)
#define FL_AP_WRITE		(1 << 10)
#define FL_AP_READ		(1 << 11)
#define FL_SHARED		(1 << 16)
#define FL_BUFFERABLE		(1 << 2)
#define FL_CACHEABLE		(1 << 3)
#define FL_TEX0			(1 << 12)
#define FL_OFFSET(va)		(((va) & 0xFFF00000) >> 20)
#define FL_NG			(1 << 17)

/* Second-level page table bits */
#define SL_BASE_MASK_LARGE	0xFFFF0000
#define SL_BASE_MASK_SMALL	0xFFFFF000
#define SL_TYPE_LARGE		(1 << 0)
#define SL_TYPE_SMALL		(2 << 0)
#define SL_AP0			(1 << 4)
#define SL_AP1			(2 << 4)
#define SL_SHARED		(1 << 10)
#define SL_BUFFERABLE		(1 << 2)
#define SL_CACHEABLE		(1 << 3)
#define SL_TEX0			(1 << 6)
#define SL_OFFSET(va)		(((va) & 0xFF000) >> 12)
#define SL_NG			(1 << 11)

/* Memory type and cache policy attributes */
#define MT_SO			0
#define MT_DEV			1
#define MT_NORMAL		2
#define CP_NONCACHED		0
#define CP_WB_WA		1
#define CP_WT			2
#define CP_WB_NWA		3

/* Global register setters / getters */
#define SET_M2VCBR_N(b, N, v)	 SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v))
#define SET_CBACR_N(b, N, v)	 SET_GLOBAL_REG_N(CBACR_N, N, (b), (v))
#define SET_TLBRSW(b, v)	 SET_GLOBAL_REG(TLBRSW, (b), (v))
#define SET_TLBTR0(b, v)	 SET_GLOBAL_REG(TLBTR0, (b), (v))
#define SET_TLBTR1(b, v)	 SET_GLOBAL_REG(TLBTR1, (b), (v))
#define SET_TLBTR2(b, v)	 SET_GLOBAL_REG(TLBTR2, (b), (v))
#define SET_TESTBUSCR(b, v)	 SET_GLOBAL_REG(TESTBUSCR, (b), (v))
#define SET_GLOBAL_TLBIALL(b, v) SET_GLOBAL_REG(GLOBAL_TLBIALL, (b), (v))
#define SET_TLBIVMID(b, v)	 SET_GLOBAL_REG(TLBIVMID, (b), (v))
#define SET_CR(b, v)		 SET_GLOBAL_REG(CR, (b), (v))
#define SET_EAR(b, v)		 SET_GLOBAL_REG(EAR, (b), (v))

Annotation

Implementation Notes