drivers/iommu/riscv/iommu-bits.h

Source file repositories/reference/linux-study-clean/drivers/iommu/riscv/iommu-bits.h

File Facts

System
Linux kernel
Corpus path
drivers/iommu/riscv/iommu-bits.h
Extension
.h
Size
31627 bytes
Lines
812
Domain
Driver Families
Bucket
drivers/iommu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct riscv_iommu_dc {
	u64 tc;
	u64 iohgatp;
	u64 ta;
	u64 fsc;
	u64 msiptp;
	u64 msi_addr_mask;
	u64 msi_addr_pattern;
	u64 _reserved;
};

/* Translation control fields */
#define RISCV_IOMMU_DC_TC_V		BIT_ULL(0)
#define RISCV_IOMMU_DC_TC_EN_ATS	BIT_ULL(1)
#define RISCV_IOMMU_DC_TC_EN_PRI	BIT_ULL(2)
#define RISCV_IOMMU_DC_TC_T2GPA		BIT_ULL(3)
#define RISCV_IOMMU_DC_TC_DTF		BIT_ULL(4)
#define RISCV_IOMMU_DC_TC_PDTV		BIT_ULL(5)
#define RISCV_IOMMU_DC_TC_PRPR		BIT_ULL(6)
#define RISCV_IOMMU_DC_TC_GADE		BIT_ULL(7)
#define RISCV_IOMMU_DC_TC_SADE		BIT_ULL(8)
#define RISCV_IOMMU_DC_TC_DPE		BIT_ULL(9)
#define RISCV_IOMMU_DC_TC_SBE		BIT_ULL(10)
#define RISCV_IOMMU_DC_TC_SXL		BIT_ULL(11)

/* Second-stage (aka G-stage) context fields */
#define RISCV_IOMMU_DC_IOHGATP_PPN	RISCV_IOMMU_ATP_PPN_FIELD
#define RISCV_IOMMU_DC_IOHGATP_GSCID	GENMASK_ULL(59, 44)
#define RISCV_IOMMU_DC_IOHGATP_MODE	RISCV_IOMMU_ATP_MODE_FIELD

/**
 * enum riscv_iommu_dc_iohgatp_modes - Guest address translation/protection modes
 * @RISCV_IOMMU_DC_IOHGATP_MODE_BARE: No translation/protection
 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4: Sv32x4 (2-bit extension of Sv32), when fctl.GXL == 1
 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4: Sv39x4 (2-bit extension of Sv39), when fctl.GXL == 0
 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4: Sv48x4 (2-bit extension of Sv48), when fctl.GXL == 0
 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4: Sv57x4 (2-bit extension of Sv57), when fctl.GXL == 0
 */
enum riscv_iommu_dc_iohgatp_modes {
	RISCV_IOMMU_DC_IOHGATP_MODE_BARE = 0,
	RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4 = 8,
	RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4 = 8,
	RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4 = 9,
	RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4 = 10
};

/* Translation attributes fields */
#define RISCV_IOMMU_DC_TA_PSCID		GENMASK_ULL(31, 12)

/* First-stage context fields */
#define RISCV_IOMMU_DC_FSC_PPN		RISCV_IOMMU_ATP_PPN_FIELD
#define RISCV_IOMMU_DC_FSC_MODE		RISCV_IOMMU_ATP_MODE_FIELD

/**
 * enum riscv_iommu_dc_fsc_atp_modes - First stage address translation/protection modes
 * @RISCV_IOMMU_DC_FSC_MODE_BARE: No translation/protection
 * @RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32: Sv32, when dc.tc.SXL == 1
 * @RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV39: Sv39, when dc.tc.SXL == 0
 * @RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV48: Sv48, when dc.tc.SXL == 0
 * @RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV57: Sv57, when dc.tc.SXL == 0
 * @RISCV_IOMMU_DC_FSC_PDTP_MODE_PD8: 1lvl PDT, 8bit process ids
 * @RISCV_IOMMU_DC_FSC_PDTP_MODE_PD17: 2lvl PDT, 17bit process ids
 * @RISCV_IOMMU_DC_FSC_PDTP_MODE_PD20: 3lvl PDT, 20bit process ids
 *
 * FSC holds IOSATP when RISCV_IOMMU_DC_TC_PDTV is 0 and PDTP otherwise.
 * IOSATP controls the first stage address translation (same as the satp register on
 * the RISC-V MMU), and PDTP holds the process directory table, used to select a
 * first stage page table based on a process id (for devices that support multiple
 * process ids).
 */
enum riscv_iommu_dc_fsc_atp_modes {
	RISCV_IOMMU_DC_FSC_MODE_BARE = 0,
	RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32 = 8,
	RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV39 = 8,
	RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV48 = 9,
	RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV57 = 10,
	RISCV_IOMMU_DC_FSC_PDTP_MODE_PD8 = 1,
	RISCV_IOMMU_DC_FSC_PDTP_MODE_PD17 = 2,
	RISCV_IOMMU_DC_FSC_PDTP_MODE_PD20 = 3
};

/* MSI page table pointer */
#define RISCV_IOMMU_DC_MSIPTP_PPN	RISCV_IOMMU_ATP_PPN_FIELD
#define RISCV_IOMMU_DC_MSIPTP_MODE	RISCV_IOMMU_ATP_MODE_FIELD
#define RISCV_IOMMU_DC_MSIPTP_MODE_OFF	0
#define RISCV_IOMMU_DC_MSIPTP_MODE_FLAT	1

/* MSI address mask */
#define RISCV_IOMMU_DC_MSI_ADDR_MASK	GENMASK_ULL(51, 0)

Annotation

Implementation Notes