drivers/iommu/tegra-smmu.c
Source file repositories/reference/linux-study-clean/drivers/iommu/tegra-smmu.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/iommu/tegra-smmu.c- Extension
.c- Size
- 28612 bytes
- Lines
- 1193
- Domain
- Driver Families
- Bucket
- drivers/iommu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitops.hlinux/debugfs.hlinux/err.hlinux/iommu.hlinux/kernel.hlinux/of.hlinux/of_platform.hlinux/pci.hlinux/platform_device.hlinux/slab.hlinux/spinlock.hlinux/dma-mapping.hsoc/tegra/ahb.hsoc/tegra/mc.hiommu-pages.h
Detected Declarations
struct tegra_smmu_groupstruct tegra_smmustruct tegra_pdstruct tegra_ptstruct tegra_smmu_asstruct tegra_pdstruct tegra_ptfunction smmu_writelfunction smmu_readlfunction iova_pd_indexfunction iova_pt_indexfunction smmu_dma_addr_validfunction smmu_pde_to_dmafunction smmu_flush_ptc_allfunction smmu_flush_ptcfunction smmu_flush_tlbfunction smmu_flush_tlb_asidfunction smmu_flush_tlb_sectionfunction smmu_flush_tlb_groupfunction smmu_flushfunction tegra_smmu_alloc_asidfunction tegra_smmu_free_asidfunction tegra_smmu_domain_freefunction tegra_smmu_find_swgroupfunction tegra_smmu_enablefunction tegra_smmu_disablefunction tegra_smmu_as_preparefunction tegra_smmu_as_unpreparefunction tegra_smmu_attach_devfunction tegra_smmu_identity_attachfunction tegra_smmu_set_pdefunction tegra_smmu_pte_get_usefunction tegra_smmu_pte_put_usefunction tegra_smmu_set_ptefunction __tegra_smmu_mapfunction __tegra_smmu_unmapfunction tegra_smmu_mapfunction tegra_smmu_unmapfunction tegra_smmu_iova_to_physfunction tegra_smmu_configurefunction tegra_smmu_find_groupfunction tegra_smmu_group_releasefunction tegra_smmu_of_xlatefunction tegra_smmu_def_domain_typefunction tegra_smmu_ahb_enablefunction tegra_smmu_swgroups_showfunction tegra_smmu_clients_showfunction tegra_smmu_debugfs_init
Annotated Snippet
struct tegra_smmu_group {
struct list_head list;
struct tegra_smmu *smmu;
const struct tegra_smmu_group_soc *soc;
struct iommu_group *group;
unsigned int swgroup;
};
struct tegra_smmu {
void __iomem *regs;
struct device *dev;
struct tegra_mc *mc;
const struct tegra_smmu_soc *soc;
struct list_head groups;
unsigned long pfn_mask;
unsigned long tlb_mask;
unsigned long *asids;
struct mutex lock;
struct list_head list;
struct dentry *debugfs;
struct iommu_device iommu; /* IOMMU Core code handle */
};
struct tegra_pd;
struct tegra_pt;
struct tegra_smmu_as {
struct iommu_domain domain;
struct tegra_smmu *smmu;
unsigned int use_count;
spinlock_t lock;
u32 *count;
struct tegra_pt **pts;
struct tegra_pd *pd;
dma_addr_t pd_dma;
unsigned id;
u32 attr;
};
static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom)
{
return container_of(dom, struct tegra_smmu_as, domain);
}
static inline void smmu_writel(struct tegra_smmu *smmu, u32 value,
unsigned long offset)
{
writel(value, smmu->regs + offset);
}
static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset)
{
return readl(smmu->regs + offset);
}
#define SMMU_CONFIG 0x010
#define SMMU_CONFIG_ENABLE (1 << 0)
#define SMMU_TLB_CONFIG 0x14
#define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29)
#define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28)
#define SMMU_TLB_CONFIG_ACTIVE_LINES(smmu) \
((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask)
#define SMMU_PTC_CONFIG 0x18
#define SMMU_PTC_CONFIG_ENABLE (1 << 29)
#define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24)
#define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f)
#define SMMU_PTB_ASID 0x01c
#define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f)
#define SMMU_PTB_DATA 0x020
#define SMMU_PTB_DATA_VALUE(dma, attr) ((dma) >> 12 | (attr))
#define SMMU_MK_PDE(dma, attr) ((dma) >> SMMU_PTE_SHIFT | (attr))
#define SMMU_TLB_FLUSH 0x030
#define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0)
#define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0)
#define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0)
#define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \
SMMU_TLB_FLUSH_VA_MATCH_SECTION)
Annotation
- Immediate include surface: `linux/bitops.h`, `linux/debugfs.h`, `linux/err.h`, `linux/iommu.h`, `linux/kernel.h`, `linux/of.h`, `linux/of_platform.h`, `linux/pci.h`.
- Detected declarations: `struct tegra_smmu_group`, `struct tegra_smmu`, `struct tegra_pd`, `struct tegra_pt`, `struct tegra_smmu_as`, `struct tegra_pd`, `struct tegra_pt`, `function smmu_writel`, `function smmu_readl`, `function iova_pd_index`.
- Atlas domain: Driver Families / drivers/iommu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.