drivers/irqchip/irq-armada-370-xp.c
Source file repositories/reference/linux-study-clean/drivers/irqchip/irq-armada-370-xp.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/irqchip/irq-armada-370-xp.c- Extension
.c- Size
- 25031 bytes
- Lines
- 918
- Domain
- Driver Families
- Bucket
- drivers/irqchip
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitfield.hlinux/bits.hlinux/err.hlinux/kernel.hlinux/module.hlinux/init.hlinux/irq.hlinux/interrupt.hlinux/irqchip.hlinux/irqchip/chained_irq.hlinux/irqchip/irq-msi-lib.hlinux/cpu.hlinux/io.hlinux/of_address.hlinux/of_irq.hlinux/of_pci.hlinux/irqdomain.hlinux/slab.hlinux/syscore_ops.hlinux/msi.hlinux/types.hasm/mach/arch.hasm/exception.hasm/smp_plat.hasm/mach/irq.h
Detected Declarations
struct mpicfunction mpic_is_ipi_availablefunction mpic_is_percpu_irqfunction mpic_irq_maskfunction mpic_irq_unmaskfunction mpic_compose_msi_msgfunction mpic_msi_set_affinityfunction mpic_msi_allocfunction mpic_msi_freefunction mpic_msi_reenable_percpufunction mpic_msi_initfunction mpic_msi_reenable_percpufunction mpic_perf_initfunction mpic_ipi_maskfunction mpic_ipi_unmaskfunction mpic_ipi_send_maskfunction mpic_ipi_ackfunction mpic_ipi_allocfunction mpic_ipi_freefunction mpic_ipi_resumefunction mpic_ipi_initfunction mpic_set_affinityfunction mpic_smp_cpu_initfunction mpic_reenable_percpufunction mpic_starting_cpufunction mpic_cascaded_starting_cpufunction mpic_smp_cpu_initfunction mpic_irq_mapfunction mpic_handle_msi_irqfunction mpic_handle_msi_irqfunction mpic_handle_ipi_irqfunction for_each_set_bitfunction mpic_handle_irqfunction mpic_suspendfunction mpic_resumefunction mpic_map_regionfunction mpic_of_init
Annotated Snippet
struct mpic {
void __iomem *base;
void __iomem *per_cpu;
int parent_irq;
struct irq_domain *domain;
#ifdef CONFIG_SMP
struct irq_domain *ipi_domain;
#endif
#ifdef CONFIG_PCI_MSI
struct irq_domain *msi_inner_domain;
DECLARE_BITMAP(msi_used, PCI_MSI_FULL_DOORBELL_NR);
struct mutex msi_lock;
phys_addr_t msi_doorbell_addr;
u32 msi_doorbell_mask;
unsigned int msi_doorbell_start, msi_doorbell_size;
#endif
u32 doorbell_mask;
};
static struct mpic *mpic_data __ro_after_init;
static inline bool mpic_is_ipi_available(struct mpic *mpic)
{
/*
* We distinguish IPI availability in the IC by the IC not having a
* parent irq defined. If a parent irq is defined, there is a parent
* interrupt controller (e.g. GIC) that takes care of inter-processor
* interrupts.
*/
return mpic->parent_irq <= 0;
}
static inline bool mpic_is_percpu_irq(irq_hw_number_t hwirq)
{
return hwirq < MPIC_PER_CPU_IRQS_NR;
}
/*
* In SMP mode:
* For shared global interrupts, mask/unmask global enable bit
* For CPU interrupts, mask/unmask the calling CPU's bit
*/
static void mpic_irq_mask(struct irq_data *d)
{
struct mpic *mpic = irq_data_get_irq_chip_data(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
if (!mpic_is_percpu_irq(hwirq))
writel(hwirq, mpic->base + MPIC_INT_CLEAR_ENABLE);
else
writel(hwirq, mpic->per_cpu + MPIC_INT_SET_MASK);
}
static void mpic_irq_unmask(struct irq_data *d)
{
struct mpic *mpic = irq_data_get_irq_chip_data(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
if (!mpic_is_percpu_irq(hwirq))
writel(hwirq, mpic->base + MPIC_INT_SET_ENABLE);
else
writel(hwirq, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
}
#ifdef CONFIG_PCI_MSI
static void mpic_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
{
unsigned int cpu = cpumask_first(irq_data_get_effective_affinity_mask(d));
struct mpic *mpic = irq_data_get_irq_chip_data(d);
msg->address_lo = lower_32_bits(mpic->msi_doorbell_addr);
msg->address_hi = upper_32_bits(mpic->msi_doorbell_addr);
msg->data = BIT(cpu + 8) | (d->hwirq + mpic->msi_doorbell_start);
}
static int mpic_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
{
unsigned int cpu;
if (!force)
cpu = cpumask_any_and(mask, cpu_online_mask);
else
cpu = cpumask_first(mask);
if (cpu >= nr_cpu_ids)
return -EINVAL;
irq_data_update_effective_affinity(d, cpumask_of(cpu));
Annotation
- Immediate include surface: `linux/bitfield.h`, `linux/bits.h`, `linux/err.h`, `linux/kernel.h`, `linux/module.h`, `linux/init.h`, `linux/irq.h`, `linux/interrupt.h`.
- Detected declarations: `struct mpic`, `function mpic_is_ipi_available`, `function mpic_is_percpu_irq`, `function mpic_irq_mask`, `function mpic_irq_unmask`, `function mpic_compose_msi_msg`, `function mpic_msi_set_affinity`, `function mpic_msi_alloc`, `function mpic_msi_free`, `function mpic_msi_reenable_percpu`.
- Atlas domain: Driver Families / drivers/irqchip.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.