drivers/irqchip/irq-ast2700-intc0.c
Source file repositories/reference/linux-study-clean/drivers/irqchip/irq-ast2700-intc0.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/irqchip/irq-ast2700-intc0.c- Extension
.c- Size
- 16944 bytes
- Lines
- 583
- Domain
- Driver Families
- Bucket
- drivers/irqchip
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitops.hlinux/device.hlinux/err.hlinux/fwnode.hlinux/io.hlinux/irq.hlinux/irqchip.hlinux/irqchip/chained_irq.hlinux/irqdomain.hlinux/kconfig.hlinux/of.hlinux/of_irq.hlinux/overflow.hlinux/property.hlinux/spinlock.hirq-ast2700.h
Detected Declarations
function Copyrightfunction aspeed_swint_irq_unmaskfunction aspeed_swint_irq_eoifunction aspeed_intc0_irq_maskfunction aspeed_intc0_irq_unmaskfunction aspeed_intc0_irq_eoifunction resolve_input_from_child_rangesfunction resolve_parent_range_for_outputfunction resolve_parent_route_for_inputfunction isfunction aspeed_intc0_irq_domain_mapfunction aspeed_intc0_irq_domain_translatefunction aspeed_intc0_irq_domain_allocfunction aspeed_intc0_irq_domain_activatefunction aspeed_intc0_disable_swintfunction aspeed_intc0_disable_intbankfunction aspeed_intc0_disable_intmfunction aspeed_intc0_probe
Annotated Snippet
if (resolved) {
resolved->start = output;
resolved->count = 1;
resolved->upstream = range.upstream;
resolved->upstream.param[ASPEED_INTC_RANGES_COUNT] +=
output - range.start;
}
return 0;
}
return -ENOENT;
}
static int resolve_parent_route_for_input(const struct aspeed_intc0 *intc0,
const struct fwnode_handle *parent, u32 input,
struct aspeed_intc_interrupt_range *resolved)
{
int rc = -ENOENT;
u32 c0o;
if (input < INT_NUM) {
static_assert(INTC0_ROUTE_NUM < INT_MAX, "Broken cast");
for (size_t i = 0; rc == -ENOENT && i < INTC0_ROUTE_NUM; i++) {
c0o = aspeed_intc0_routes[input / INTC0_IRQS_PER_BANK][i];
if (c0o == AST2700_INTC_INVALID_ROUTE)
continue;
if (input < GIC_P2P_SPI_END)
c0o += input % INTC0_IRQS_PER_BANK;
rc = resolve_parent_range_for_output(intc0, parent, c0o, resolved);
if (!rc)
return (int)i;
}
} else if (input < (INT_NUM + INTM_NUM)) {
c0o = aspeed_intc0_intm_routes[(input - INT_NUM) / INTM_IRQS_PER_BANK];
c0o += ((input - INT_NUM) % INTM_IRQS_PER_BANK);
return resolve_parent_range_for_output(intc0, parent, c0o, resolved);
} else if (input < (INT_NUM + INTM_NUM + SWINT_NUM)) {
c0o = input - SWINT_BASE + INTC0_SWINT_OUT_BASE;
return resolve_parent_range_for_output(intc0, parent, c0o, resolved);
} else {
return -ENOENT;
}
return rc;
}
/**
* aspeed_intc0_resolve_route - Determine the necessary interrupt output at intc1
* @c0domain: The pointer to intc0's irq_domain
* @nc1outs: The number of valid intc1 outputs available for the input
* @c1outs: The array of available intc1 output indices for the input
* @nc1ranges: The number of interrupt range entries for intc1
* @c1ranges: The array of configured intc1 interrupt ranges
* @resolved: The fully resolved range entry after applying the resolution
* algorithm
*
* Returns: The intc1 route index associated with the intc1 output identified in
* @resolved on success. Otherwise, a negative errno value.
*
* The AST2700 interrupt architecture allows any peripheral interrupt source
* to be routed to one of up to four processors running in the SoC. A processor
* binding a driver for a peripheral that requests an interrupt is (without
* further design and effort) the destination for the requested interrupt.
*
* Routing a peripheral interrupt to its destination processor requires
* coordination between INTC0 on the CPU die and one or more INTC1 instances.
* At least one INTC1 instance exists in the SoC on the IO-die, however up
* to two more instances may be integrated via LTPI (LVDS Tunneling Protocol
* & Interface).
*
* Between the multiple destinations, various route constraints, and the
* devicetree binding design, some information that's needed at INTC1 instances
* to route inbound interrupts correctly to the destination processor is only
* available at INTC0.
*
* aspeed_intc0_resolve_route() is to be invoked by INTC1 driver instances to
* perform the route resolution. The implementation in INTC0 allows INTC0 to
* encapsulate the information used to perform route selection, and provides it
* with an opportunity to apply policy as part of the selection process. Such
* policy may, for instance, choose to de-prioritise some interrupts destined
* for the PSP (Primary Service Processor) GIC.
*/
int aspeed_intc0_resolve_route(const struct irq_domain *c0domain, size_t nc1outs,
const u32 *c1outs, size_t nc1ranges,
const struct aspeed_intc_interrupt_range *c1ranges,
struct aspeed_intc_interrupt_range *resolved)
{
Annotation
- Immediate include surface: `linux/bitops.h`, `linux/device.h`, `linux/err.h`, `linux/fwnode.h`, `linux/io.h`, `linux/irq.h`, `linux/irqchip.h`, `linux/irqchip/chained_irq.h`.
- Detected declarations: `function Copyright`, `function aspeed_swint_irq_unmask`, `function aspeed_swint_irq_eoi`, `function aspeed_intc0_irq_mask`, `function aspeed_intc0_irq_unmask`, `function aspeed_intc0_irq_eoi`, `function resolve_input_from_child_ranges`, `function resolve_parent_range_for_output`, `function resolve_parent_route_for_input`, `function is`.
- Atlas domain: Driver Families / drivers/irqchip.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.