drivers/irqchip/irq-loongarch-cpu.c

Source file repositories/reference/linux-study-clean/drivers/irqchip/irq-loongarch-cpu.c

File Facts

System
Linux kernel
Corpus path
drivers/irqchip/irq-loongarch-cpu.c
Extension
.c
Size
4284 bytes
Lines
180
Domain
Driver Families
Bucket
drivers/irqchip
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>

#include <asm/loongarch.h>
#include <asm/setup.h>

#include "irq-loongson.h"

static struct irq_domain *irq_domain;
struct fwnode_handle *cpuintc_handle;

static u32 lpic_gsi_to_irq(u32 gsi)
{
	int irq = 0;

	/* Only pch irqdomain transferring is required for LoongArch. */
	if (gsi >= GSI_MIN_PCH_IRQ && gsi <= GSI_MAX_PCH_IRQ)
		irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH);

	return (irq > 0) ? irq : 0;
}

static struct fwnode_handle *lpic_get_gsi_domain_id(u32 gsi)
{
	int id;
	struct fwnode_handle *domain_handle = NULL;

	switch (gsi) {
	case GSI_MIN_CPU_IRQ ... GSI_MAX_CPU_IRQ:
		if (liointc_handle)
			domain_handle = liointc_handle;
		break;

	case GSI_MIN_LPC_IRQ ... GSI_MAX_LPC_IRQ:
		if (pch_lpc_handle)
			domain_handle = pch_lpc_handle;
		break;

	case GSI_MIN_PCH_IRQ ... GSI_MAX_PCH_IRQ:
		id = find_pch_pic(gsi);
		if (id >= 0 && pch_pic_handle[id])
			domain_handle = pch_pic_handle[id];
		break;
	}

	return domain_handle;
}

static void mask_loongarch_irq(struct irq_data *d)
{
	clear_csr_ecfg(ECFGF(d->hwirq));
}

static void unmask_loongarch_irq(struct irq_data *d)
{
	set_csr_ecfg(ECFGF(d->hwirq));
}

static struct irq_chip cpu_irq_controller = {
	.name		= "CPUINTC",
	.irq_mask	= mask_loongarch_irq,
	.irq_unmask	= unmask_loongarch_irq,
};

static void handle_cpu_irq(struct pt_regs *regs)
{
	int hwirq;
	unsigned int estat = read_csr_estat() & CSR_ESTAT_IS;

	while ((hwirq = ffs(estat))) {
		estat &= ~BIT(hwirq - 1);
		generic_handle_domain_irq(irq_domain, hwirq - 1);
	}
}

static int loongarch_cpu_intc_map(struct irq_domain *d, unsigned int irq,
			     irq_hw_number_t hwirq)
{
	irq_set_noprobe(irq);
	irq_set_chip_and_handler(irq, &cpu_irq_controller, handle_percpu_irq);

Annotation

Implementation Notes