drivers/irqchip/irq-realtek-rtl.c

Source file repositories/reference/linux-study-clean/drivers/irqchip/irq-realtek-rtl.c

File Facts

System
Linux kernel
Corpus path
drivers/irqchip/irq-realtek-rtl.c
Extension
.c
Size
5162 bytes
Lines
201
Domain
Driver Families
Bucket
drivers/irqchip
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2020 Birger Koblitz <mail@birger-koblitz.de>
 * Copyright (C) 2020 Bert Vermeulen <bert@biot.com>
 * Copyright (C) 2020 John Crispin <john@phrozen.org>
 */

#include <linux/of_irq.h>
#include <linux/irqchip.h>
#include <linux/spinlock.h>
#include <linux/of_address.h>
#include <linux/irqchip/chained_irq.h>

/* Global Interrupt Mask Register */
#define RTL_ICTL_GIMR		0x00
/* Global Interrupt Status Register */
#define RTL_ICTL_GISR		0x04
/* Interrupt Routing Registers */
#define RTL_ICTL_IRR0		0x08
#define RTL_ICTL_IRR1		0x0c
#define RTL_ICTL_IRR2		0x10
#define RTL_ICTL_IRR3		0x14

#define RTL_ICTL_NUM_INPUTS	32

#define REG(cpu, x)		(realtek_ictl_base[cpu] + x)

static DEFINE_RAW_SPINLOCK(irq_lock);
static void __iomem *realtek_ictl_base[NR_CPUS];

/*
 * IRR0-IRR3 store 4 bits per interrupt, but Realtek uses inverted numbering,
 * placing IRQ 31 in the first four bits. A routing value of '0' means the
 * interrupt is left disconnected. Routing values {1..15} connect to output
 * lines {0..14}.
 */
#define IRR_OFFSET(idx)		(4 * (3 - (idx * 4) / 32))
#define IRR_SHIFT(idx)		((idx * 4) % 32)

static inline void enable_gimr(unsigned int cpu, unsigned int hw_irq)
{
	u32 gimr;

	gimr = readl(REG(cpu, RTL_ICTL_GIMR));
	gimr |= BIT(hw_irq);
	writel(gimr, REG(cpu, RTL_ICTL_GIMR));
}

static inline void disable_gimr(unsigned int cpu, unsigned int hw_irq)
{
	u32 gimr;

	gimr = readl(REG(cpu, RTL_ICTL_GIMR));
	gimr &= ~BIT(hw_irq);
	writel(gimr, REG(cpu, RTL_ICTL_GIMR));
}

static void write_irr(unsigned int cpu, int hw_irq, u32 value)
{
	void __iomem *irr0 = REG(cpu, RTL_ICTL_IRR0);
	unsigned int offset = IRR_OFFSET(hw_irq);
	unsigned int shift = IRR_SHIFT(hw_irq);
	u32 irr;

	irr = readl(irr0 + offset) & ~(0xf << shift);
	irr |= (value & 0xf) << shift;
	writel(irr, irr0 + offset);
}

static void realtek_ictl_unmask_irq(struct irq_data *i)
{
	unsigned int cpu;

	guard(raw_spinlock)(&irq_lock);
	for_each_cpu(cpu, irq_data_get_effective_affinity_mask(i))
		enable_gimr(cpu, i->hwirq);
}

static void realtek_ictl_mask_irq(struct irq_data *i)
{
	unsigned int cpu;

	guard(raw_spinlock)(&irq_lock);
	for_each_cpu(cpu, irq_data_get_effective_affinity_mask(i))
		disable_gimr(cpu, i->hwirq);
}

static int realtek_ictl_irq_affinity(struct irq_data *i, const struct cpumask *dest, bool force)
{
	if (!irqd_irq_masked(i))

Annotation

Implementation Notes