drivers/irqchip/irq-renesas-intc-irqpin.c
Source file repositories/reference/linux-study-clean/drivers/irqchip/irq-renesas-intc-irqpin.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/irqchip/irq-renesas-intc-irqpin.c- Extension
.c- Size
- 16282 bytes
- Lines
- 609
- Domain
- Driver Families
- Bucket
- drivers/irqchip
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/init.hlinux/of.hlinux/platform_device.hlinux/spinlock.hlinux/interrupt.hlinux/ioport.hlinux/io.hlinux/irq.hlinux/irqdomain.hlinux/err.hlinux/slab.hlinux/module.hlinux/pm_runtime.h
Detected Declarations
struct intc_irqpin_iomemstruct intc_irqpin_irqstruct intc_irqpin_privstruct intc_irqpin_configfunction intc_irqpin_read32function intc_irqpin_read8function intc_irqpin_write32function intc_irqpin_write8function intc_irqpin_readfunction intc_irqpin_writefunction intc_irqpin_hwirq_maskfunction intc_irqpin_irq_write_hwirqfunction intc_irqpin_read_modify_writefunction intc_irqpin_mask_unmask_priofunction intc_irqpin_set_sensefunction intc_irqpin_dbgfunction intc_irqpin_irq_enablefunction intc_irqpin_irq_disablefunction intc_irqpin_shared_irq_enablefunction intc_irqpin_shared_irq_disablefunction intc_irqpin_irq_enable_forcefunction intc_irqpin_irq_disable_forcefunction intc_irqpin_irq_set_typefunction intc_irqpin_irq_set_wakefunction intc_irqpin_irq_handlerfunction intc_irqpin_shared_irq_handlerfunction intc_irqpin_irq_domain_mapfunction intc_irqpin_probefunction intc_irqpin_removefunction intc_irqpin_suspendfunction intc_irqpin_initfunction intc_irqpin_exit
Annotated Snippet
struct intc_irqpin_iomem {
void __iomem *iomem;
unsigned long (*read)(void __iomem *iomem);
void (*write)(void __iomem *iomem, unsigned long data);
int width;
};
struct intc_irqpin_irq {
int hw_irq;
int requested_irq;
int domain_irq;
struct intc_irqpin_priv *p;
};
struct intc_irqpin_priv {
struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
unsigned int sense_bitfield_width;
struct platform_device *pdev;
struct irq_chip irq_chip;
struct irq_domain *irq_domain;
atomic_t wakeup_path;
unsigned shared_irqs:1;
u8 shared_irq_mask;
};
struct intc_irqpin_config {
int irlm_bit; /* -1 if non-existent */
};
static unsigned long intc_irqpin_read32(void __iomem *iomem)
{
return ioread32(iomem);
}
static unsigned long intc_irqpin_read8(void __iomem *iomem)
{
return ioread8(iomem);
}
static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
{
iowrite32(data, iomem);
}
static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
{
iowrite8(data, iomem);
}
static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
int reg)
{
struct intc_irqpin_iomem *i = &p->iomem[reg];
return i->read(i->iomem);
}
static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
int reg, unsigned long data)
{
struct intc_irqpin_iomem *i = &p->iomem[reg];
i->write(i->iomem, data);
}
static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
int reg, int hw_irq)
{
return BIT((p->iomem[reg].width - 1) - hw_irq);
}
static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
int reg, int hw_irq)
{
intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
}
static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
int reg, int shift,
int width, int value)
{
unsigned long flags;
unsigned long tmp;
raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
tmp = intc_irqpin_read(p, reg);
Annotation
- Immediate include surface: `linux/init.h`, `linux/of.h`, `linux/platform_device.h`, `linux/spinlock.h`, `linux/interrupt.h`, `linux/ioport.h`, `linux/io.h`, `linux/irq.h`.
- Detected declarations: `struct intc_irqpin_iomem`, `struct intc_irqpin_irq`, `struct intc_irqpin_priv`, `struct intc_irqpin_config`, `function intc_irqpin_read32`, `function intc_irqpin_read8`, `function intc_irqpin_write32`, `function intc_irqpin_write8`, `function intc_irqpin_read`, `function intc_irqpin_write`.
- Atlas domain: Driver Families / drivers/irqchip.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.