drivers/leds/flash/leds-tps6131x.c

Source file repositories/reference/linux-study-clean/drivers/leds/flash/leds-tps6131x.c

File Facts

System
Linux kernel
Corpus path
drivers/leds/flash/leds-tps6131x.c
Extension
.c
Size
24821 bytes
Lines
816
Domain
Driver Families
Bucket
drivers/leds
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct tps6131x {
	struct device *dev;
	struct regmap *regmap;
	struct gpio_desc *reset_gpio;
	/*
	 * Registers 0, 1, 2, and 3 control parts of the controller that are not completely
	 * independent of each other. Since some operations require the registers to be written in
	 * a specific order to avoid unwanted side effects, they are synchronized with a lock.
	 */
	struct mutex lock; /* Hardware access lock for register 0, 1, 2 and 3 */
	struct delayed_work torch_refresh_work;
	bool valley_current_limit;
	bool chan1_en;
	bool chan2_en;
	bool chan3_en;
	struct fwnode_handle *led_node;
	u32 max_flash_current_ma;
	u32 step_flash_current_ma;
	u32 max_torch_current_ma;
	u32 step_torch_current_ma;
	u32 max_timeout_us;
	struct led_classdev_flash fled_cdev;
	struct v4l2_flash *v4l2_flash;
};

static struct tps6131x *fled_cdev_to_tps6131x(struct led_classdev_flash *fled_cdev)
{
	return container_of(fled_cdev, struct tps6131x, fled_cdev);
}

/*
 * Register contents after a power on/reset. These values cannot be changed.
 */

#define TPS6131X_DCLC2_50MA	     2
#define TPS6131X_DCLC13_25MA	     1
#define TPS6131X_FC2_400MA	     16
#define TPS6131X_FC13_200MA	     8
#define TPS6131X_STIM_0_579MS_1_37MS 6
#define TPS6131X_SELSTIM_RANGE0	     0
#define TPS6131X_INDC_OFF	     0
#define TPS6131X_OV_4950MV	     9
#define TPS6131X_BATDROOP_150MV	     4

static const struct reg_default tps6131x_regmap_defaults[] = {
	{ TPS6131X_REG_0, (TPS6131X_DCLC13_25MA << TPS6131X_REG_0_DCLC13_SHIFT) |
				  (TPS6131X_DCLC2_50MA << TPS6131X_REG_0_DCLC2_SHIFT) },
	{ TPS6131X_REG_1, (TPS6131X_MODE_SHUTDOWN << TPS6131X_REG_1_MODE_SHIFT) |
				  (TPS6131X_FC2_400MA << TPS6131X_REG_1_FC2_SHIFT) },
	{ TPS6131X_REG_2, (TPS6131X_MODE_SHUTDOWN << TPS6131X_REG_2_MODE_SHIFT) |
				  (TPS6131X_FC13_200MA << TPS6131X_REG_2_FC13_SHIFT) },
	{ TPS6131X_REG_3, (TPS6131X_STIM_0_579MS_1_37MS << TPS6131X_REG_3_STIM_SHIFT) |
				  (TPS6131X_SELSTIM_RANGE0 << TPS6131X_REG_3_SELSTIM_TO) |
				  TPS6131X_REG_3_TXMASK },
	{ TPS6131X_REG_4, (TPS6131X_INDC_OFF << TPS6131X_REG_4_INDC_SHIFT) },
	{ TPS6131X_REG_5, TPS6131X_REG_5_ENPSM | TPS6131X_REG_5_STSTRB1_DIR |
				  TPS6131X_REG_5_GPIOTYPE | TPS6131X_REG_5_ENLED2 },
	{ TPS6131X_REG_6, (TPS6131X_OV_4950MV << TPS6131X_REG_6_OV_SHIFT) },
	{ TPS6131X_REG_7, (TPS6131X_BATDROOP_150MV << TPS6131X_REG_7_BATDROOP_SHIFT) },
};

/*
 * These registers contain flags that are reset when read.
 */
static bool tps6131x_regmap_precious(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TPS6131X_REG_3:
	case TPS6131X_REG_4:
	case TPS6131X_REG_6:
		return true;
	default:
		return false;
	}
}

static const struct regmap_config tps6131x_regmap = {
	.reg_bits = 8,
	.val_bits = 8,
	.max_register = TPS6131X_REG_7,
	.reg_defaults = tps6131x_regmap_defaults,
	.num_reg_defaults = ARRAY_SIZE(tps6131x_regmap_defaults),
	.cache_type = REGCACHE_FLAT,
	.precious_reg = &tps6131x_regmap_precious,
};

struct tps6131x_timer_config {
	u8 val;
	u8 range;
	u32 time_us;

Annotation

Implementation Notes