drivers/mailbox/arm_mhuv3.c

Source file repositories/reference/linux-study-clean/drivers/mailbox/arm_mhuv3.c

File Facts

System
Linux kernel
Corpus path
drivers/mailbox/arm_mhuv3.c
Extension
.c
Size
28209 bytes
Lines
1104
Domain
Driver Families
Bucket
drivers/mailbox
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct blk_id {
#define id		GENMASK(3, 0)
	u32 val;
} __packed;

struct feat_spt0 {
#define	dbe_spt		GENMASK(3, 0)
#define	fe_spt		GENMASK(7, 4)
#define	fce_spt		GENMASK(11, 8)
	u32 val;
} __packed;

struct feat_spt1 {
#define	auto_op_spt	GENMASK(3, 0)
	u32 val;
} __packed;

struct dbch_cfg0 {
#define num_dbch	GENMASK(7, 0)
	u32 val;
} __packed;

struct ffch_cfg0 {
#define num_ffch	GENMASK(7, 0)
#define x8ba_spt	BIT(8)
#define x16ba_spt	BIT(9)
#define x32ba_spt	BIT(10)
#define x64ba_spt	BIT(11)
#define ffch_depth	GENMASK(25, 16)
	u32 val;
} __packed;

struct fch_cfg0 {
#define num_fch		GENMASK(9, 0)
#define fcgi_spt	BIT(10)		// MBX-only
#define num_fcg		GENMASK(15, 11)
#define num_fch_per_grp	GENMASK(20, 16)
#define fch_ws		GENMASK(28, 21)
	u32 val;
} __packed;

struct ctrl {
#define op_req		BIT(0)
#define	ch_op_mask	BIT(1)
	u32 val;
} __packed;

struct fch_ctrl {
#define _int_en		BIT(2)
	u32 val;
} __packed;

struct iidr {
#define implementer	GENMASK(11, 0)
#define revision	GENMASK(15, 12)
#define variant		GENMASK(19, 16)
#define product_id	GENMASK(31, 20)
	u32 val;
} __packed;

struct aidr {
#define arch_minor_rev	GENMASK(3, 0)
#define arch_major_rev	GENMASK(7, 4)
	u32 val;
} __packed;

struct ctrl_page {
	struct blk_id blk_id;
	u8 pad[12];
	struct feat_spt0 feat_spt0;
	struct feat_spt1 feat_spt1;
	u8 pad1[8];
	struct dbch_cfg0 dbch_cfg0;
	u8 pad2[12];
	struct ffch_cfg0 ffch_cfg0;
	u8 pad3[12];
	struct fch_cfg0 fch_cfg0;
	u8 pad4[188];
	struct ctrl x_ctrl;
	/*-- MBX-only registers --*/
	u8 pad5[60];
	struct fch_ctrl fch_ctrl;
	u32 fcg_int_en;
	u8 pad6[696];
	/*-- End of MBX-only ---- */
	u32 dbch_int_st[MHUV3_DBCH_CMB_INT_ST_REG_CNT];
	u32 ffch_int_st[MHUV3_FFCH_CMB_INT_ST_REG_CNT];
	/*-- MBX-only registers --*/
	u8 pad7[88];
	u32 fcg_int_st;

Annotation

Implementation Notes