drivers/mailbox/bcm-flexrm-mailbox.c
Source file repositories/reference/linux-study-clean/drivers/mailbox/bcm-flexrm-mailbox.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/mailbox/bcm-flexrm-mailbox.c- Extension
.c- Size
- 45477 bytes
- Lines
- 1674
- Domain
- Driver Families
- Bucket
- drivers/mailbox
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
asm/barrier.hasm/byteorder.hlinux/atomic.hlinux/bitmap.hlinux/debugfs.hlinux/delay.hlinux/device.hlinux/dma-mapping.hlinux/dmapool.hlinux/err.hlinux/interrupt.hlinux/kernel.hlinux/mailbox_controller.hlinux/mailbox/brcm-message.hlinux/module.hlinux/msi.hlinux/of_address.hlinux/of_irq.hlinux/platform_device.hlinux/spinlock.h
Detected Declarations
struct flexrm_ringstruct flexrm_mboxfunction flexrm_read_descfunction flexrm_write_descfunction flexrm_cmpl_desc_to_reqidfunction flexrm_cmpl_desc_to_errorfunction flexrm_is_next_table_descfunction flexrm_next_table_descfunction flexrm_null_descfunction flexrm_estimate_header_desc_countfunction flexrm_flip_header_togglefunction flexrm_header_descfunction flexrm_enqueue_descfunction bitsfunction flexrm_src_descfunction flexrm_msrc_descfunction flexrm_dst_descfunction flexrm_mdst_descfunction flexrm_imm_descfunction flexrm_srct_descfunction flexrm_dstt_descfunction flexrm_immt_descfunction flexrm_spu_sanity_checkfunction flexrm_spu_estimate_nonheader_desc_countfunction flexrm_spu_dma_mapfunction flexrm_spu_dma_unmapfunction flexrm_sba_sanity_checkfunction flexrm_sba_estimate_nonheader_desc_countfunction flexrm_sanity_checkfunction flexrm_estimate_nonheader_desc_countfunction flexrm_dma_mapfunction flexrm_dma_unmapfunction flexrm_write_config_in_seqfilefunction flexrm_write_stats_in_seqfilefunction flexrm_new_requestfunction flexrm_process_completionsfunction flexrm_debugfs_conf_showfunction flexrm_debugfs_stats_showfunction flexrm_irq_threadfunction flexrm_send_datafunction flexrm_peek_datafunction flexrm_startupfunction flexrm_shutdownfunction flexrm_mbox_msi_writefunction flexrm_mbox_probefunction flexrm_mbox_remove
Annotated Snippet
struct flexrm_ring {
/* Unprotected members */
int num;
struct flexrm_mbox *mbox;
void __iomem *regs;
bool irq_requested;
unsigned int irq;
cpumask_t irq_aff_hint;
unsigned int msi_timer_val;
unsigned int msi_count_threshold;
struct brcm_message *requests[RING_MAX_REQ_COUNT];
void *bd_base;
dma_addr_t bd_dma_base;
u32 bd_write_offset;
void *cmpl_base;
dma_addr_t cmpl_dma_base;
/* Atomic stats */
atomic_t msg_send_count;
atomic_t msg_cmpl_count;
/* Protected members */
spinlock_t lock;
DECLARE_BITMAP(requests_bmap, RING_MAX_REQ_COUNT);
u32 cmpl_read_offset;
};
struct flexrm_mbox {
struct device *dev;
void __iomem *regs;
u32 num_rings;
struct flexrm_ring *rings;
struct dma_pool *bd_pool;
struct dma_pool *cmpl_pool;
struct dentry *root;
struct mbox_controller controller;
};
/* ====== FlexRM ring descriptor helper routines ===== */
static u64 flexrm_read_desc(void *desc_ptr)
{
return le64_to_cpu(*((u64 *)desc_ptr));
}
static void flexrm_write_desc(void *desc_ptr, u64 desc)
{
*((u64 *)desc_ptr) = cpu_to_le64(desc);
}
static u32 flexrm_cmpl_desc_to_reqid(u64 cmpl_desc)
{
return (u32)(cmpl_desc & CMPL_OPAQUE_MASK);
}
static int flexrm_cmpl_desc_to_error(u64 cmpl_desc)
{
u32 status;
status = DESC_DEC(cmpl_desc, CMPL_DME_STATUS_SHIFT,
CMPL_DME_STATUS_MASK);
if (status & DME_STATUS_ERROR_MASK)
return -EIO;
status = DESC_DEC(cmpl_desc, CMPL_RM_STATUS_SHIFT,
CMPL_RM_STATUS_MASK);
status &= RM_STATUS_CODE_MASK;
if (status == RM_STATUS_CODE_AE_TIMEOUT)
return -ETIMEDOUT;
return 0;
}
static bool flexrm_is_next_table_desc(void *desc_ptr)
{
u64 desc = flexrm_read_desc(desc_ptr);
u32 type = DESC_DEC(desc, DESC_TYPE_SHIFT, DESC_TYPE_MASK);
return (type == NPTR_TYPE) ? true : false;
}
static u64 flexrm_next_table_desc(u32 toggle, dma_addr_t next_addr)
{
u64 desc = 0;
DESC_ENC(desc, NPTR_TYPE, DESC_TYPE_SHIFT, DESC_TYPE_MASK);
DESC_ENC(desc, toggle, NPTR_TOGGLE_SHIFT, NPTR_TOGGLE_MASK);
DESC_ENC(desc, next_addr, NPTR_ADDR_SHIFT, NPTR_ADDR_MASK);
return desc;
}
Annotation
- Immediate include surface: `asm/barrier.h`, `asm/byteorder.h`, `linux/atomic.h`, `linux/bitmap.h`, `linux/debugfs.h`, `linux/delay.h`, `linux/device.h`, `linux/dma-mapping.h`.
- Detected declarations: `struct flexrm_ring`, `struct flexrm_mbox`, `function flexrm_read_desc`, `function flexrm_write_desc`, `function flexrm_cmpl_desc_to_reqid`, `function flexrm_cmpl_desc_to_error`, `function flexrm_is_next_table_desc`, `function flexrm_next_table_desc`, `function flexrm_null_desc`, `function flexrm_estimate_header_desc_count`.
- Atlas domain: Driver Families / drivers/mailbox.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.