drivers/mailbox/Kconfig
Source file repositories/reference/linux-study-clean/drivers/mailbox/Kconfig
File Facts
- System
- Linux kernel
- Corpus path
drivers/mailbox/Kconfig- Extension
[no extension]- Size
- 14563 bytes
- Lines
- 403
- Domain
- Driver Families
- Bucket
- drivers/mailbox
- Inferred role
- Driver Families: build/configuration rule
- Status
- atlas-only
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: GPL-2.0-only
menuconfig MAILBOX
bool "Mailbox Hardware Support"
help
Mailbox is a framework to control hardware communication between
on-chip processors through queued messages and interrupt driven
signals. Say Y if your platform supports hardware mailboxes.
if MAILBOX
config ARM_MHU
tristate "ARM MHU Mailbox"
depends on ARM_AMBA
help
Say Y here if you want to build the ARM MHU controller driver.
The controller has 3 mailbox channels, the last of which can be
used in Secure mode only.
config ARM_MHU_V2
tristate "ARM MHUv2 Mailbox"
depends on ARM_AMBA
help
Say Y here if you want to build the ARM MHUv2 controller driver,
which provides unidirectional mailboxes between processing elements.
config ARM_MHU_V3
tristate "ARM MHUv3 Mailbox"
depends on ARM64 || COMPILE_TEST
depends on HAS_IOMEM || COMPILE_TEST
depends on OF
help
Say Y here if you want to build the ARM MHUv3 controller driver,
which provides unidirectional mailboxes between processing elements.
ARM MHUv3 controllers can implement a varying number of extensions
that provides different means of transports: supported extensions
will be discovered and possibly managed at probe-time.
config AST2700_MBOX
tristate "ASPEED AST2700 IPC driver"
depends on ARCH_ASPEED || COMPILE_TEST
help
Mailbox driver implementation for ASPEED AST27XX SoCs. This driver
can be used to send message between different processors in SoC.
The driver provides mailbox support for sending interrupts to the
clients. Say Y here if you want to build this driver.
config CV1800_MBOX
tristate "cv1800 mailbox"
depends on ARCH_SOPHGO || COMPILE_TEST
help
Mailbox driver implementation for Sophgo CV18XX SoCs. This driver
can be used to send message between different processors in SoC. Any
processer can write data in a channel, and set co-responding register
to raise interrupt to notice another processor, and it is allowed to
send data to itself.
config EXYNOS_MBOX
tristate "Exynos Mailbox"
depends on ARCH_EXYNOS || COMPILE_TEST
help
Say Y here if you want to build the Samsung Exynos Mailbox controller
driver. The controller has 16 flag bits for hardware interrupt
generation and a shared register for passing mailbox messages.
When the controller is used by the ACPM interface the shared register
is ignored and the mailbox controller acts as a doorbell that raises
the interrupt to the ACPM firmware.
config IMX_MBOX
tristate "i.MX Mailbox"
Annotation
- Atlas domain: Driver Families / drivers/mailbox.
- Implementation status: atlas-only.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.