drivers/mailbox/mailbox-th1520.c
Source file repositories/reference/linux-study-clean/drivers/mailbox/mailbox-th1520.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/mailbox/mailbox-th1520.c- Extension
.c- Size
- 16138 bytes
- Lines
- 598
- Domain
- Driver Families
- Bucket
- drivers/mailbox
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk.hlinux/interrupt.hlinux/io.hlinux/kernel.hlinux/mailbox_controller.hlinux/module.hlinux/of_device.hlinux/platform_device.hlinux/slab.h
Detected Declarations
struct th1520_mbox_contextstruct th1520_mbox_con_privstruct th1520_mbox_privenum th1520_mbox_icu_cpu_idfunction to_th1520_mbox_privfunction th1520_mbox_writefunction th1520_mbox_readfunction th1520_mbox_rmwfunction th1520_mbox_chan_writefunction th1520_mbox_chan_readfunction th1520_mbox_chan_rmwfunction th1520_mbox_chan_rd_datafunction th1520_mbox_chan_wr_datafunction th1520_mbox_chan_wr_ackfunction th1520_mbox_chan_id_to_mapbitfunction th1520_mbox_isrfunction th1520_mbox_send_datafunction th1520_mbox_startupfunction th1520_mbox_shutdownfunction th1520_mbox_init_genericfunction th1520_disable_clkfunction th1520_mbox_probefunction th1520_mbox_suspend_noirqfunction th1520_mbox_resume_noirqfunction th1520_mbox_runtime_suspendfunction th1520_mbox_runtime_resume
Annotated Snippet
struct th1520_mbox_context {
u32 intr_mask[TH_1520_MBOX_CHANS];
};
#endif
enum th1520_mbox_icu_cpu_id {
TH_1520_MBOX_ICU_KERNEL_CPU0, /* 910T */
TH_1520_MBOX_ICU_CPU1, /* 902 */
TH_1520_MBOX_ICU_CPU2, /* 906 */
TH_1520_MBOX_ICU_CPU3, /* 910R */
};
struct th1520_mbox_con_priv {
enum th1520_mbox_icu_cpu_id idx;
void __iomem *comm_local_base;
void __iomem *comm_remote_base;
char irq_desc[TH_1520_MBOX_CHAN_NAME_SIZE];
struct mbox_chan *chan;
};
struct th1520_mbox_priv {
struct device *dev;
void __iomem *local_icu[TH_1520_MBOX_CHANS];
void __iomem *remote_icu[TH_1520_MBOX_CHANS - 1];
void __iomem *cur_cpu_ch_base;
spinlock_t mbox_lock; /* control register lock */
struct mbox_controller mbox;
struct mbox_chan mbox_chans[TH_1520_MBOX_CHANS];
struct clk_bulk_data clocks[TH_1520_MBOX_CHANS];
struct th1520_mbox_con_priv con_priv[TH_1520_MBOX_CHANS];
int irq;
#ifdef CONFIG_PM_SLEEP
struct th1520_mbox_context *ctx;
#endif
};
static struct th1520_mbox_priv *
to_th1520_mbox_priv(struct mbox_controller *mbox)
{
return container_of(mbox, struct th1520_mbox_priv, mbox);
}
static void th1520_mbox_write(struct th1520_mbox_priv *priv, u32 val, u32 offs)
{
iowrite32(val, priv->cur_cpu_ch_base + offs);
}
static u32 th1520_mbox_read(struct th1520_mbox_priv *priv, u32 offs)
{
return ioread32(priv->cur_cpu_ch_base + offs);
}
static u32 th1520_mbox_rmw(struct th1520_mbox_priv *priv, u32 off, u32 set,
u32 clr)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&priv->mbox_lock, flags);
val = th1520_mbox_read(priv, off);
val &= ~clr;
val |= set;
th1520_mbox_write(priv, val, off);
spin_unlock_irqrestore(&priv->mbox_lock, flags);
return val;
}
static void th1520_mbox_chan_write(struct th1520_mbox_con_priv *cp, u32 val,
u32 offs, bool is_remote)
{
if (is_remote)
iowrite32(val, cp->comm_remote_base + offs);
else
iowrite32(val, cp->comm_local_base + offs);
}
static u32 th1520_mbox_chan_read(struct th1520_mbox_con_priv *cp, u32 offs,
bool is_remote)
{
if (is_remote)
return ioread32(cp->comm_remote_base + offs);
else
return ioread32(cp->comm_local_base + offs);
}
static void th1520_mbox_chan_rmw(struct th1520_mbox_con_priv *cp, u32 off,
u32 set, u32 clr, bool is_remote)
{
Annotation
- Immediate include surface: `linux/clk.h`, `linux/interrupt.h`, `linux/io.h`, `linux/kernel.h`, `linux/mailbox_controller.h`, `linux/module.h`, `linux/of_device.h`, `linux/platform_device.h`.
- Detected declarations: `struct th1520_mbox_context`, `struct th1520_mbox_con_priv`, `struct th1520_mbox_priv`, `enum th1520_mbox_icu_cpu_id`, `function to_th1520_mbox_priv`, `function th1520_mbox_write`, `function th1520_mbox_read`, `function th1520_mbox_rmw`, `function th1520_mbox_chan_write`, `function th1520_mbox_chan_read`.
- Atlas domain: Driver Families / drivers/mailbox.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.