drivers/mailbox/pcc.c
Source file repositories/reference/linux-study-clean/drivers/mailbox/pcc.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/mailbox/pcc.c- Extension
.c- Size
- 24201 bytes
- Lines
- 898
- Domain
- Driver Families
- Bucket
- drivers/mailbox
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/acpi.hlinux/delay.hlinux/io.hlinux/init.hlinux/interrupt.hlinux/list.hlinux/log2.hlinux/platform_device.hlinux/mailbox_controller.hlinux/mailbox_client.hlinux/io-64-nonatomic-lo-hi.hacpi/pcc.h
Detected Declarations
struct pcc_chan_regstruct pcc_chan_infofunction read_registerfunction write_registerfunction pcc_chan_reg_readfunction pcc_chan_reg_writefunction pcc_chan_reg_read_modify_writefunction pcc_map_interruptfunction pcc_chan_plat_irq_can_be_sharedfunction pcc_mbox_cmd_complete_checkfunction pcc_mbox_error_check_and_clearfunction pcc_chan_acknowledgefunction pcc_mbox_irqfunction pcc_mbox_request_channelfunction pcc_mbox_request_channelfunction pcc_send_datafunction pcc_last_tx_donefunction pcc_startupfunction pcc_shutdownfunction parse_pcc_subspacefunction pcc_chan_reg_initfunction typesfunction pcc_parse_subspace_db_regfunction pcc_parse_subspace_shmemfunction acpi_pcc_probefunction pcc_mbox_probefunction pcc_initexport pcc_mbox_request_channelexport pcc_mbox_free_channel
Annotated Snippet
struct pcc_chan_reg {
void __iomem *vaddr;
struct acpi_generic_address *gas;
u64 preserve_mask;
u64 set_mask;
u64 status_mask;
};
/**
* struct pcc_chan_info - PCC channel specific information
*
* @chan: PCC channel information with Shared Memory Region info
* @db: PCC register bundle for the doorbell register
* @plat_irq_ack: PCC register bundle for the platform interrupt acknowledge
* register
* @cmd_complete: PCC register bundle for the command complete check register
* @cmd_update: PCC register bundle for the command complete update register
* @error: PCC register bundle for the error status register
* @plat_irq: platform interrupt
* @type: PCC subspace type
* @plat_irq_flags: platform interrupt flags
* @chan_in_use: this flag is used just to check if the interrupt needs
* handling when it is shared. Since only one transfer can occur
* at a time and mailbox takes care of locking, this flag can be
* accessed without a lock. Note: the type only support the
* communication from OSPM to Platform, like type3, use it, and
* other types completely ignore it.
*/
struct pcc_chan_info {
struct pcc_mbox_chan chan;
struct pcc_chan_reg db;
struct pcc_chan_reg plat_irq_ack;
struct pcc_chan_reg cmd_complete;
struct pcc_chan_reg cmd_update;
struct pcc_chan_reg error;
int plat_irq;
u8 type;
unsigned int plat_irq_flags;
bool chan_in_use;
};
#define to_pcc_chan_info(c) container_of(c, struct pcc_chan_info, chan)
static struct pcc_chan_info *chan_info;
static int pcc_chan_count;
/*
* PCC can be used with perf critical drivers such as CPPC
* So it makes sense to locally cache the virtual address and
* use it to read/write to PCC registers such as doorbell register
*
* The below read_register and write_registers are used to read and
* write from perf critical registers such as PCC doorbell register
*/
static void read_register(void __iomem *vaddr, u64 *val, unsigned int bit_width)
{
switch (bit_width) {
case 8:
*val = readb(vaddr);
break;
case 16:
*val = readw(vaddr);
break;
case 32:
*val = readl(vaddr);
break;
case 64:
*val = readq(vaddr);
break;
}
}
static void write_register(void __iomem *vaddr, u64 val, unsigned int bit_width)
{
switch (bit_width) {
case 8:
writeb(val, vaddr);
break;
case 16:
writew(val, vaddr);
break;
case 32:
writel(val, vaddr);
break;
case 64:
writeq(val, vaddr);
break;
}
}
static int pcc_chan_reg_read(struct pcc_chan_reg *reg, u64 *val)
Annotation
- Immediate include surface: `linux/acpi.h`, `linux/delay.h`, `linux/io.h`, `linux/init.h`, `linux/interrupt.h`, `linux/list.h`, `linux/log2.h`, `linux/platform_device.h`.
- Detected declarations: `struct pcc_chan_reg`, `struct pcc_chan_info`, `function read_register`, `function write_register`, `function pcc_chan_reg_read`, `function pcc_chan_reg_write`, `function pcc_chan_reg_read_modify_write`, `function pcc_map_interrupt`, `function pcc_chan_plat_irq_can_be_shared`, `function pcc_mbox_cmd_complete_check`.
- Atlas domain: Driver Families / drivers/mailbox.
- Implementation status: integration implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.