drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c

Source file repositories/reference/linux-study-clean/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c

File Facts

System
Linux kernel
Corpus path
drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c
Extension
.c
Size
77015 bytes
Lines
3520
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cxd2880_tnrdmd_ts_clk_cfg {
	u8 srl_clk_mode;
	u8 srl_duty_mode;
	u8 ts_clk_period;
};

static int set_ts_clk_mode_and_freq(struct cxd2880_tnrdmd *tnr_dmd,
				    enum cxd2880_dtv_sys sys)
{
	int ret;
	u8 backwards_compatible = 0;
	struct cxd2880_tnrdmd_ts_clk_cfg ts_clk_cfg;
	u8 ts_rate_ctrl_off = 0;
	u8 ts_in_off = 0;
	u8 ts_clk_manaul_on = 0;
	u8 data = 0;

	static const struct cxd2880_tnrdmd_ts_clk_cfg srl_ts_clk_stgs[2][2] = {
		{
			{3, 1, 8,},
			{0, 2, 16,}
		}, {
			{1, 1, 8,},
			{2, 2, 16,}
		}
	};

	if (!tnr_dmd)
		return -EINVAL;

	ret = tnr_dmd->io->write_reg(tnr_dmd->io,
				     CXD2880_IO_TGT_DMD,
				     0x00, 0x00);
	if (ret)
		return ret;

	if (tnr_dmd->is_ts_backwards_compatible_mode) {
		backwards_compatible = 1;
		ts_rate_ctrl_off = 1;
		ts_in_off = 1;
	} else {
		backwards_compatible = 0;
		ts_rate_ctrl_off = 0;
		ts_in_off = 0;
	}

	if (tnr_dmd->ts_byte_clk_manual_setting) {
		ts_clk_manaul_on = 1;
		ts_rate_ctrl_off = 0;
	}

	ret = cxd2880_io_set_reg_bits(tnr_dmd->io,
				      CXD2880_IO_TGT_DMD,
				      0xd3, ts_rate_ctrl_off, 0x01);
	if (ret)
		return ret;

	ret = cxd2880_io_set_reg_bits(tnr_dmd->io,
				      CXD2880_IO_TGT_DMD,
				      0xde, ts_in_off, 0x01);
	if (ret)
		return ret;

	ret = cxd2880_io_set_reg_bits(tnr_dmd->io,
				      CXD2880_IO_TGT_DMD,
				      0xda, ts_clk_manaul_on, 0x01);
	if (ret)
		return ret;

	ts_clk_cfg = srl_ts_clk_stgs[tnr_dmd->srl_ts_clk_mod_cnts]
				    [tnr_dmd->srl_ts_clk_frq];

	if (tnr_dmd->ts_byte_clk_manual_setting)
		ts_clk_cfg.ts_clk_period = tnr_dmd->ts_byte_clk_manual_setting;

	ret = cxd2880_io_set_reg_bits(tnr_dmd->io,
				      CXD2880_IO_TGT_DMD,
				      0xc4, ts_clk_cfg.srl_clk_mode, 0x03);
	if (ret)
		return ret;

	ret = cxd2880_io_set_reg_bits(tnr_dmd->io,
				      CXD2880_IO_TGT_DMD,
				      0xd1, ts_clk_cfg.srl_duty_mode, 0x03);
	if (ret)
		return ret;

	ret = tnr_dmd->io->write_reg(tnr_dmd->io,
				     CXD2880_IO_TGT_DMD, 0xd9,
				     ts_clk_cfg.ts_clk_period);

Annotation

Implementation Notes