drivers/media/dvb-frontends/drxd_firm.c

Source file repositories/reference/linux-study-clean/drivers/media/dvb-frontends/drxd_firm.c

File Facts

System
Linux kernel
Corpus path
drivers/media/dvb-frontends/drxd_firm.c
Extension
.c
Size
35730 bytes
Lines
914
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * drxd_firm.c : DRXD firmware tables
 *
 * Copyright (C) 2006-2007 Micronas
 */

/* TODO: generate this file with a script from a settings file */

/* Contains A2 firmware version: 1.4.2
 * Contains B1 firmware version: 3.3.33
 * Contains settings from driver 1.4.23
*/

#include "drxd_firm.h"

#define ADDRESS(x)     ((x) & 0xFF), (((x)>>8) & 0xFF), (((x)>>16) & 0xFF), (((x)>>24) & 0xFF)
#define LENGTH(x)      ((x) & 0xFF), (((x)>>8) & 0xFF)

/* Is written via block write, must be little endian */
#define DATA16(x)      ((x) & 0xFF), (((x)>>8) & 0xFF)

#define WRBLOCK(a, l) ADDRESS(a), LENGTH(l)
#define WR16(a, d) ADDRESS(a), LENGTH(1), DATA16(d)

#define END_OF_TABLE      0xFF, 0xFF, 0xFF, 0xFF

/* HI firmware patches */

#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
#define HI_TR_FUNC_SIZE 9	/* size of this function in instruction words */

u8 DRXD_InitAtomicRead[] = {
	WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE),
	0x26, 0x00,		/* 0         -> ring.rdy;           */
	0x60, 0x04,		/* r0rami.dt -> ring.xba;           */
	0x61, 0x04,		/* r0rami.dt -> ring.xad;           */
	0xE3, 0x07,		/* HI_RA_RAM_USR_BEGIN -> ring.iad; */
	0x40, 0x00,		/* (long immediate)                 */
	0x64, 0x04,		/* r0rami.dt -> ring.len;           */
	0x65, 0x04,		/* r0rami.dt -> ring.ctl;           */
	0x26, 0x00,		/* 0         -> ring.rdy;           */
	0x38, 0x00,		/* 0         -> jumps.ad;           */
	END_OF_TABLE
};

/* Pins D0 and D1 of the parallel MPEG output can be used
   to set the I2C address of a device. */

#define HI_RST_FUNC_ADDR (HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE)
#define HI_RST_FUNC_SIZE 54	/* size of this function in instruction words */

/* D0 Version */
u8 DRXD_HiI2cPatch_1[] = {
	WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
	0xC8, 0x07, 0x01, 0x00,	/* MASK      -> reg0.dt;                        */
	0xE0, 0x07, 0x15, 0x02,	/* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
	0xE1, 0x07, 0x12, 0x00,	/* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
	0xA2, 0x00,		/* M_BNK_ID_DAT -> ring.iba;                    */
	0x23, 0x00,		/* &data     -> ring.iad;                       */
	0x24, 0x00,		/* 0         -> ring.len;                       */
	0xA5, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
	0x26, 0x00,		/* 0         -> ring.rdy;                       */
	0x42, 0x00,		/* &data+1   -> w0ram.ad;                       */
	0xC0, 0x07, 0xFF, 0x0F,	/* -1        -> w0ram.dt;                       */
	0x63, 0x00,		/* &data+1   -> ring.iad;                       */
	0x65, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
	0x26, 0x00,		/* 0         -> ring.rdy;                       */
	0xE1, 0x07, 0x38, 0x00,	/* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad;    */
	0xA5, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
	0x26, 0x00,		/* 0         -> ring.rdy;                       */
	0xE1, 0x07, 0x12, 0x00,	/* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
	0x23, 0x00,		/* &data     -> ring.iad;                       */
	0x65, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
	0x26, 0x00,		/* 0         -> ring.rdy;                       */
	0x42, 0x00,		/* &data+1   -> w0ram.ad;                       */
	0x0F, 0x04,		/* r0ram.dt  -> and.op;                         */
	0x1C, 0x06,		/* reg0.dt   -> and.tr;                         */
	0xCF, 0x04,		/* and.rs    -> add.op;                         */
	0xD0, 0x07, 0x70, 0x00,	/* DEF_DEV_ID -> add.tr;                        */
	0xD0, 0x04,		/* add.rs    -> add.tr;                         */
	0xC8, 0x04,		/* add.rs    -> reg0.dt;                        */
	0x60, 0x00,		/* reg0.dt   -> w0ram.dt;                       */
	0xC2, 0x07, 0x10, 0x00,	/* SLV0_BASE -> w0rami.ad;                      */
	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
	0x01, 0x06,		/* reg0.dt   -> w0rami.dt;                      */
	0xC2, 0x07, 0x20, 0x00,	/* SLV1_BASE -> w0rami.ad;                      */
	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
	0x01, 0x06,		/* reg0.dt   -> w0rami.dt;                      */
	0xC2, 0x07, 0x30, 0x00,	/* CMD_BASE  -> w0rami.ad;                      */

Annotation

Implementation Notes