drivers/media/dvb-frontends/drxk_map.h
Source file repositories/reference/linux-study-clean/drivers/media/dvb-frontends/drxk_map.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/media/dvb-frontends/drxk_map.h- Extension
.h- Size
- 37485 bytes
- Lines
- 456
- Domain
- Driver Families
- Bucket
- drivers/media
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#define AUD_COMM_EXEC__A 0x1000000
#define AUD_COMM_EXEC_STOP 0x0
#define FEC_COMM_EXEC__A 0x1C00000
#define FEC_COMM_EXEC_STOP 0x0
#define FEC_COMM_EXEC_ACTIVE 0x1
#define FEC_DI_COMM_EXEC__A 0x1C20000
#define FEC_DI_COMM_EXEC_STOP 0x0
#define FEC_DI_INPUT_CTL__A 0x1C20016
#define FEC_RS_COMM_EXEC__A 0x1C30000
#define FEC_RS_COMM_EXEC_STOP 0x0
#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012
#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013
#define FEC_RS_NR_BIT_ERRORS__A 0x1C30014
#define FEC_OC_MODE__A 0x1C40011
#define FEC_OC_MODE_PARITY__M 0x1
#define FEC_OC_DTO_MODE__A 0x1C40014
#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1
#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4
#define FEC_OC_DTO_PERIOD__A 0x1C40015
#define FEC_OC_DTO_BURST_LEN__A 0x1C40018
#define FEC_OC_FCT_MODE__A 0x1C4001A
#define FEC_OC_FCT_MODE__PRE 0x0
#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1
#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2
#define FEC_OC_TMD_MODE__A 0x1C4001E
#define FEC_OC_TMD_COUNT__A 0x1C4001F
#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020
#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021
#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023
#define FEC_OC_AVR_PARM_A__A 0x1C40026
#define FEC_OC_AVR_PARM_B__A 0x1C40027
#define FEC_OC_RCN_GAIN__A 0x1C4002E
#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030
#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032
#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033
#define FEC_OC_SNC_MODE__A 0x1C40040
#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10
#define FEC_OC_SNC_LWM__A 0x1C40041
#define FEC_OC_SNC_HWM__A 0x1C40042
#define FEC_OC_SNC_UNLOCK__A 0x1C40043
#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046
#define FEC_OC_IPR_MODE__A 0x1C40048
#define FEC_OC_IPR_MODE_SERIAL__M 0x1
#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4
#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10
#define FEC_OC_IPR_INVERT__A 0x1C40049
#define FEC_OC_IPR_INVERT_MD0__M 0x1
#define FEC_OC_IPR_INVERT_MD1__M 0x2
#define FEC_OC_IPR_INVERT_MD2__M 0x4
#define FEC_OC_IPR_INVERT_MD3__M 0x8
#define FEC_OC_IPR_INVERT_MD4__M 0x10
#define FEC_OC_IPR_INVERT_MD5__M 0x20
#define FEC_OC_IPR_INVERT_MD6__M 0x40
#define FEC_OC_IPR_INVERT_MD7__M 0x80
#define FEC_OC_IPR_INVERT_MERR__M 0x100
#define FEC_OC_IPR_INVERT_MSTRT__M 0x200
#define FEC_OC_IPR_INVERT_MVAL__M 0x400
#define FEC_OC_IPR_INVERT_MCLK__M 0x800
#define FEC_OC_OCR_INVERT__A 0x1C40052
#define IQM_COMM_EXEC__A 0x1800000
#define IQM_COMM_EXEC_B_STOP 0x0
#define IQM_COMM_EXEC_B_ACTIVE 0x1
#define IQM_FS_RATE_OFS_LO__A 0x1820010
#define IQM_FS_ADJ_SEL__A 0x1820014
#define IQM_FS_ADJ_SEL_B_OFF 0x0
#define IQM_FS_ADJ_SEL_B_QAM 0x1
#define IQM_FS_ADJ_SEL_B_VSB 0x2
#define IQM_FD_RATESEL__A 0x1830010
#define IQM_RC_RATE_OFS_LO__A 0x1840010
#define IQM_RC_RATE_OFS_LO__W 16
#define IQM_RC_RATE_OFS_LO__M 0xFFFF
#define IQM_RC_RATE_OFS_HI__M 0xFF
#define IQM_RC_ADJ_SEL__A 0x1840014
#define IQM_RC_ADJ_SEL_B_OFF 0x0
#define IQM_RC_ADJ_SEL_B_QAM 0x1
#define IQM_RC_ADJ_SEL_B_VSB 0x2
#define IQM_RC_STRETCH__A 0x1840016
#define IQM_CF_COMM_INT_MSK__A 0x1860006
#define IQM_CF_SYMMETRIC__A 0x1860010
#define IQM_CF_MIDTAP__A 0x1860011
#define IQM_CF_MIDTAP_RE__B 0
#define IQM_CF_MIDTAP_IM__B 1
#define IQM_CF_OUT_ENA__A 0x1860012
#define IQM_CF_OUT_ENA_QAM__B 1
#define IQM_CF_OUT_ENA_OFDM__M 0x4
#define IQM_CF_ADJ_SEL__A 0x1860013
#define IQM_CF_SCALE__A 0x1860014
#define IQM_CF_SCALE_SH__A 0x1860015
#define IQM_CF_SCALE_SH__PRE 0x0
#define IQM_CF_POW_MEAS_LEN__A 0x1860017Annotation
- Atlas domain: Driver Families / drivers/media.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.