drivers/media/dvb-frontends/rtl2832.c

Source file repositories/reference/linux-study-clean/drivers/media/dvb-frontends/rtl2832.c

File Facts

System
Linux kernel
Corpus path
drivers/media/dvb-frontends/rtl2832.c
Extension
.c
Size
28716 bytes
Lines
1149
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Realtek RTL2832 DVB-T demodulator driver
 *
 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
 * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
 */

#include "rtl2832_priv.h"

#define REG_MASK(b) (BIT(b + 1) - 1)

static const struct rtl2832_reg_entry registers[] = {
	[DVBT_SOFT_RST]		= {0x101,  2, 2},
	[DVBT_IIC_REPEAT]	= {0x101,  3, 3},
	[DVBT_TR_WAIT_MIN_8K]	= {0x188, 11, 2},
	[DVBT_RSD_BER_FAIL_VAL]	= {0x18f, 15, 0},
	[DVBT_EN_BK_TRK]	= {0x1a6,  7, 7},
	[DVBT_AD_EN_REG]	= {0x008,  7, 7},
	[DVBT_AD_EN_REG1]	= {0x008,  6, 6},
	[DVBT_EN_BBIN]		= {0x1b1,  0, 0},
	[DVBT_MGD_THD0]		= {0x195,  7, 0},
	[DVBT_MGD_THD1]		= {0x196,  7, 0},
	[DVBT_MGD_THD2]		= {0x197,  7, 0},
	[DVBT_MGD_THD3]		= {0x198,  7, 0},
	[DVBT_MGD_THD4]		= {0x199,  7, 0},
	[DVBT_MGD_THD5]		= {0x19a,  7, 0},
	[DVBT_MGD_THD6]		= {0x19b,  7, 0},
	[DVBT_MGD_THD7]		= {0x19c,  7, 0},
	[DVBT_EN_CACQ_NOTCH]	= {0x161,  4, 4},
	[DVBT_AD_AV_REF]	= {0x009,  6, 0},
	[DVBT_REG_PI]		= {0x00a,  2, 0},
	[DVBT_PIP_ON]		= {0x021,  3, 3},
	[DVBT_SCALE1_B92]	= {0x292,  7, 0},
	[DVBT_SCALE1_B93]	= {0x293,  7, 0},
	[DVBT_SCALE1_BA7]	= {0x2a7,  7, 0},
	[DVBT_SCALE1_BA9]	= {0x2a9,  7, 0},
	[DVBT_SCALE1_BAA]	= {0x2aa,  7, 0},
	[DVBT_SCALE1_BAB]	= {0x2ab,  7, 0},
	[DVBT_SCALE1_BAC]	= {0x2ac,  7, 0},
	[DVBT_SCALE1_BB0]	= {0x2b0,  7, 0},
	[DVBT_SCALE1_BB1]	= {0x2b1,  7, 0},
	[DVBT_KB_P1]		= {0x164,  3, 1},
	[DVBT_KB_P2]		= {0x164,  6, 4},
	[DVBT_KB_P3]		= {0x165,  2, 0},
	[DVBT_OPT_ADC_IQ]	= {0x006,  5, 4},
	[DVBT_AD_AVI]		= {0x009,  1, 0},
	[DVBT_AD_AVQ]		= {0x009,  3, 2},
	[DVBT_K1_CR_STEP12]	= {0x2ad,  9, 4},
	[DVBT_TRK_KS_P2]	= {0x16f,  2, 0},
	[DVBT_TRK_KS_I2]	= {0x170,  5, 3},
	[DVBT_TR_THD_SET2]	= {0x172,  3, 0},
	[DVBT_TRK_KC_P2]	= {0x173,  5, 3},
	[DVBT_TRK_KC_I2]	= {0x175,  2, 0},
	[DVBT_CR_THD_SET2]	= {0x176,  7, 6},
	[DVBT_PSET_IFFREQ]	= {0x119, 21, 0},
	[DVBT_SPEC_INV]		= {0x115,  0, 0},
	[DVBT_RSAMP_RATIO]	= {0x19f, 27, 2},
	[DVBT_CFREQ_OFF_RATIO]	= {0x19d, 23, 4},
	[DVBT_FSM_STAGE]	= {0x351,  6, 3},
	[DVBT_RX_CONSTEL]	= {0x33c,  3, 2},
	[DVBT_RX_HIER]		= {0x33c,  6, 4},
	[DVBT_RX_C_RATE_LP]	= {0x33d,  2, 0},
	[DVBT_RX_C_RATE_HP]	= {0x33d,  5, 3},
	[DVBT_GI_IDX]		= {0x351,  1, 0},
	[DVBT_FFT_MODE_IDX]	= {0x351,  2, 2},
	[DVBT_RSD_BER_EST]	= {0x34e, 15, 0},
	[DVBT_CE_EST_EVM]	= {0x40c, 15, 0},
	[DVBT_RF_AGC_VAL]	= {0x35b, 13, 0},
	[DVBT_IF_AGC_VAL]	= {0x359, 13, 0},
	[DVBT_DAGC_VAL]		= {0x305,  7, 0},
	[DVBT_SFREQ_OFF]	= {0x318, 13, 0},
	[DVBT_CFREQ_OFF]	= {0x35f, 17, 0},
	[DVBT_POLAR_RF_AGC]	= {0x00e,  1, 1},
	[DVBT_POLAR_IF_AGC]	= {0x00e,  0, 0},
	[DVBT_AAGC_HOLD]	= {0x104,  5, 5},
	[DVBT_EN_RF_AGC]	= {0x104,  6, 6},
	[DVBT_EN_IF_AGC]	= {0x104,  7, 7},
	[DVBT_IF_AGC_MIN]	= {0x108,  7, 0},
	[DVBT_IF_AGC_MAX]	= {0x109,  7, 0},
	[DVBT_RF_AGC_MIN]	= {0x10a,  7, 0},
	[DVBT_RF_AGC_MAX]	= {0x10b,  7, 0},
	[DVBT_IF_AGC_MAN]	= {0x10c,  6, 6},
	[DVBT_IF_AGC_MAN_VAL]	= {0x10c, 13, 0},
	[DVBT_RF_AGC_MAN]	= {0x10e,  6, 6},
	[DVBT_RF_AGC_MAN_VAL]	= {0x10e, 13, 0},
	[DVBT_DAGC_TRG_VAL]	= {0x112,  7, 0},
	[DVBT_AGC_TARG_VAL_0]	= {0x102,  0, 0},
	[DVBT_AGC_TARG_VAL_8_1]	= {0x103,  7, 0},
	[DVBT_AAGC_LOOP_GAIN]	= {0x1c7,  5, 1},

Annotation

Implementation Notes