drivers/media/i2c/adv7343_regs.h

Source file repositories/reference/linux-study-clean/drivers/media/i2c/adv7343_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/media/i2c/adv7343_regs.h
Extension
.h
Size
5227 bytes
Lines
174
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct adv7343_std_info {
	u32 standard_val3;
	u32 fsc_val;
	v4l2_std_id stdid;
};

/* Register offset macros */
#define ADV7343_POWER_MODE_REG		(0x00)
#define ADV7343_MODE_SELECT_REG		(0x01)
#define ADV7343_MODE_REG0		(0x02)

#define ADV7343_DAC2_OUTPUT_LEVEL	(0x0b)

#define ADV7343_SOFT_RESET		(0x17)

#define ADV7343_HD_MODE_REG1		(0x30)
#define ADV7343_HD_MODE_REG2		(0x31)
#define ADV7343_HD_MODE_REG3		(0x32)
#define ADV7343_HD_MODE_REG4		(0x33)
#define ADV7343_HD_MODE_REG5		(0x34)
#define ADV7343_HD_MODE_REG6		(0x35)

#define ADV7343_HD_MODE_REG7		(0x39)

#define ADV7343_SD_MODE_REG1		(0x80)
#define ADV7343_SD_MODE_REG2		(0x82)
#define ADV7343_SD_MODE_REG3		(0x83)
#define ADV7343_SD_MODE_REG4		(0x84)
#define ADV7343_SD_MODE_REG5		(0x86)
#define ADV7343_SD_MODE_REG6		(0x87)
#define ADV7343_SD_MODE_REG7		(0x88)
#define ADV7343_SD_MODE_REG8		(0x89)

#define ADV7343_FSC_REG0		(0x8C)
#define ADV7343_FSC_REG1		(0x8D)
#define ADV7343_FSC_REG2		(0x8E)
#define ADV7343_FSC_REG3		(0x8F)

#define ADV7343_SD_CGMS_WSS0		(0x99)

#define ADV7343_SD_HUE_REG		(0xA0)
#define ADV7343_SD_BRIGHTNESS_WSS	(0xA1)

/* Default values for the registers */
#define ADV7343_POWER_MODE_REG_DEFAULT		(0x10)
#define ADV7343_HD_MODE_REG1_DEFAULT		(0x3C)	/* Changed Default
							   720p EAVSAV code*/
#define ADV7343_HD_MODE_REG2_DEFAULT		(0x01)	/* Changed Pixel data
							   valid */
#define ADV7343_HD_MODE_REG3_DEFAULT		(0x00)	/* Color delay 0 clks */
#define ADV7343_HD_MODE_REG4_DEFAULT		(0xE8)	/* Changed */
#define ADV7343_HD_MODE_REG5_DEFAULT		(0x08)
#define ADV7343_HD_MODE_REG6_DEFAULT		(0x00)
#define ADV7343_HD_MODE_REG7_DEFAULT		(0x00)
#define ADV7343_SD_MODE_REG8_DEFAULT		(0x00)
#define ADV7343_SOFT_RESET_DEFAULT		(0x02)
#define ADV7343_COMPOSITE_POWER_VALUE		(0x80)
#define ADV7343_COMPONENT_POWER_VALUE		(0x1C)
#define ADV7343_SVIDEO_POWER_VALUE		(0x60)
#define ADV7343_SD_HUE_REG_DEFAULT		(127)
#define ADV7343_SD_BRIGHTNESS_WSS_DEFAULT	(0x03)

#define ADV7343_SD_CGMS_WSS0_DEFAULT		(0x10)

#define ADV7343_SD_MODE_REG1_DEFAULT		(0x00)
#define ADV7343_SD_MODE_REG2_DEFAULT		(0xC9)
#define ADV7343_SD_MODE_REG3_DEFAULT		(0x10)
#define ADV7343_SD_MODE_REG4_DEFAULT		(0x01)
#define ADV7343_SD_MODE_REG5_DEFAULT		(0x02)
#define ADV7343_SD_MODE_REG6_DEFAULT		(0x0C)
#define ADV7343_SD_MODE_REG7_DEFAULT		(0x04)
#define ADV7343_SD_MODE_REG8_DEFAULT		(0x00)

/* Bit masks for Mode Select Register */
#define INPUT_MODE_MASK			(0x70)
#define SD_INPUT_MODE			(0x00)
#define HD_720P_INPUT_MODE		(0x10)
#define HD_1080I_INPUT_MODE		(0x10)

/* Bit masks for Mode Register 0 */
#define TEST_PATTERN_BLACK_BAR_EN	(0x04)
#define YUV_OUTPUT_SELECT		(0x20)
#define RGB_OUTPUT_SELECT		(0xDF)

/* Bit masks for DAC output levels */
#define DAC_OUTPUT_LEVEL_MASK		(0xFF)

/* Bit masks for soft reset register */
#define SOFT_RESET			(0x02)

Annotation

Implementation Notes