drivers/media/i2c/ccs-pll.h

Source file repositories/reference/linux-study-clean/drivers/media/i2c/ccs-pll.h

File Facts

System
Linux kernel
Corpus path
drivers/media/i2c/ccs-pll.h
Extension
.h
Size
7341 bytes
Lines
236
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ccs_pll_branch_fr {
	u16 pre_pll_clk_div;
	u16 pll_multiplier;
	u32 pll_ip_clk_freq_hz;
	u32 pll_op_clk_freq_hz;
};

/**
 * struct ccs_pll_branch_bk - CCS PLL configuration (back)
 *
 * A single branch back-end of the CCS PLL tree.
 *
 * @sys_clk_div: System clock divider
 * @pix_clk_div: Pixel clock divider
 * @sys_clk_freq_hz: System clock frequency
 * @pix_clk_freq_hz: Pixel clock frequency
 */
struct ccs_pll_branch_bk {
	u16 sys_clk_div;
	u16 pix_clk_div;
	u32 sys_clk_freq_hz;
	u32 pix_clk_freq_hz;
};

/**
 * struct ccs_pll - Full CCS PLL configuration
 *
 * All information required to calculate CCS PLL configuration.
 *
 * @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input)
 * @op_lanes: Number of operational lanes (input)
 * @vt_lanes: Number of video timing lanes (input)
 * @csi2: CSI-2 related parameters
 * @csi2.lanes: The number of the CSI-2 data lanes (input)
 * @binning_vertical: Vertical binning factor (input)
 * @binning_horizontal: Horizontal binning factor (input)
 * @scale_m: Downscaling factor, M component, [16, max] (input)
 * @scale_n: Downscaling factor, N component, typically 16 (input)
 * @bits_per_pixel: Bits per pixel on the output data bus (input)
 * @op_bits_per_lane: Number of bits per OP lane (input)
 * @flags: CCS_PLL_FLAG_* (input)
 * @link_freq: Chosen link frequency (input)
 * @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock
 *		     (input)
 * @vt_fr: Video timing front-end configuration (output)
 * @vt_bk: Video timing back-end configuration (output)
 * @op_fr: Operational timing front-end configuration (output)
 * @op_bk: Operational timing back-end configuration (output)
 * @pixel_rate_csi: Pixel rate on the output data bus (output)
 * @pixel_rate_pixel_array: Nominal pixel rate in the sensor's pixel array
 *			    (output)
 */
struct ccs_pll {
	/* input values */
	u8 bus_type;
	u8 op_lanes;
	u8 vt_lanes;
	struct {
		u8 lanes;
	} csi2;
	u8 binning_horizontal;
	u8 binning_vertical;
	u8 scale_m;
	u8 scale_n;
	u8 bits_per_pixel;
	u8 op_bits_per_lane;
	u16 flags;
	u32 link_freq;
	u32 ext_clk_freq_hz;

	/* output values */
	struct ccs_pll_branch_fr vt_fr;
	struct ccs_pll_branch_bk vt_bk;
	struct ccs_pll_branch_fr op_fr;
	struct ccs_pll_branch_bk op_bk;

	u32 pixel_rate_csi;
	u32 pixel_rate_pixel_array;
};

/**
 * struct ccs_pll_branch_limits_fr - CCS PLL front-end limits
 *
 * @min_pre_pll_clk_div: Minimum pre-PLL clock divider
 * @max_pre_pll_clk_div: Maximum pre-PLL clock divider
 * @min_pll_ip_clk_freq_hz: Minimum PLL input clock frequency
 * @max_pll_ip_clk_freq_hz: Maximum PLL input clock frequency
 * @min_pll_multiplier: Minimum PLL multiplier
 * @max_pll_multiplier: Maximum PLL multiplier
 * @min_pll_op_clk_freq_hz: Minimum PLL output clock frequency

Annotation

Implementation Notes