drivers/media/i2c/ov13858.c

Source file repositories/reference/linux-study-clean/drivers/media/i2c/ov13858.c

File Facts

System
Linux kernel
Corpus path
drivers/media/i2c/ov13858.c
Extension
.c
Size
38783 bytes
Lines
1782
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ov13858_reg {
	u16 address;
	u8 val;
};

struct ov13858_reg_list {
	u32 num_of_regs;
	const struct ov13858_reg *regs;
};

/* Link frequency config */
struct ov13858_link_freq_config {
	u32 pixels_per_line;

	/* PLL registers for this link frequency */
	struct ov13858_reg_list reg_list;
};

/* Mode : resolution and related config&values */
struct ov13858_mode {
	/* Frame width */
	u32 width;
	/* Frame height */
	u32 height;

	/* V-timing */
	u32 vts_def;
	u32 vts_min;

	/* Index of Link frequency config to be used */
	u32 link_freq_index;
	/* Default register values */
	struct ov13858_reg_list reg_list;
};

/* 4224x3136 needs 1080Mbps/lane, 4 lanes */
static const struct ov13858_reg mipi_data_rate_1080mbps[] = {
	/* PLL1 registers */
	{OV13858_REG_PLL1_CTRL_0, 0x07},
	{OV13858_REG_PLL1_CTRL_1, 0x01},
	{OV13858_REG_PLL1_CTRL_2, 0xc2},
	{OV13858_REG_PLL1_CTRL_3, 0x00},
	{OV13858_REG_PLL1_CTRL_4, 0x00},
	{OV13858_REG_PLL1_CTRL_5, 0x01},

	/* PLL2 registers */
	{OV13858_REG_PLL2_CTRL_B, 0x05},
	{OV13858_REG_PLL2_CTRL_C, 0x01},
	{OV13858_REG_PLL2_CTRL_D, 0x0e},
	{OV13858_REG_PLL2_CTRL_E, 0x05},
	{OV13858_REG_PLL2_CTRL_F, 0x01},
	{OV13858_REG_PLL2_CTRL_12, 0x01},
	{OV13858_REG_MIPI_SC_CTRL0, 0x72},
	{OV13858_REG_MIPI_SC_CTRL1, 0x01},
};

/*
 * 2112x1568, 2112x1188, 1056x784 need 540Mbps/lane,
 * 4 lanes
 */
static const struct ov13858_reg mipi_data_rate_540mbps[] = {
	/* PLL1 registers */
	{OV13858_REG_PLL1_CTRL_0, 0x07},
	{OV13858_REG_PLL1_CTRL_1, 0x01},
	{OV13858_REG_PLL1_CTRL_2, 0xc2},
	{OV13858_REG_PLL1_CTRL_3, 0x01},
	{OV13858_REG_PLL1_CTRL_4, 0x00},
	{OV13858_REG_PLL1_CTRL_5, 0x01},

	/* PLL2 registers */
	{OV13858_REG_PLL2_CTRL_B, 0x05},
	{OV13858_REG_PLL2_CTRL_C, 0x01},
	{OV13858_REG_PLL2_CTRL_D, 0x0e},
	{OV13858_REG_PLL2_CTRL_E, 0x05},
	{OV13858_REG_PLL2_CTRL_F, 0x01},
	{OV13858_REG_PLL2_CTRL_12, 0x01},
	{OV13858_REG_MIPI_SC_CTRL0, 0x72},
	{OV13858_REG_MIPI_SC_CTRL1, 0x01},
};

static const struct ov13858_reg mode_4224x3136_regs[] = {
	{0x3013, 0x32},
	{0x301b, 0xf0},
	{0x301f, 0xd0},
	{0x3106, 0x15},
	{0x3107, 0x23},
	{0x350a, 0x00},
	{0x350e, 0x00},
	{0x3510, 0x00},
	{0x3511, 0x02},

Annotation

Implementation Notes