drivers/media/i2c/ov8865.c

Source file repositories/reference/linux-study-clean/drivers/media/i2c/ov8865.c

File Facts

System: Linux kernel
Corpus path: drivers/media/i2c/ov8865.c
Extension: .c
Size: 81215 bytes
Lines: 3145
Domain: Driver Families
Bucket: drivers/media
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
Allocates kernel memory; connect allocation flags and lifetime to context constraints.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/clk.h
linux/delay.h
linux/device.h
linux/i2c.h
linux/mod_devicetable.h
linux/module.h
linux/of_graph.h
linux/pm_runtime.h
linux/regulator/consumer.h
linux/videodev2.h
media/v4l2-ctrls.h
media/v4l2-device.h
media/v4l2-fwnode.h
media/v4l2-image-sizes.h
media/v4l2-mediabus.h

Detected Declarations

struct ov8865_register_value
struct ov8865_pll1_config
struct ov8865_pll2_config
struct ov8865_sclk_config
struct ov8865_pll_configs
struct ov8865_mode
struct ov8865_state
struct ov8865_ctrls
struct ov8865_sensor
enum extclk_rate
function ov8865_read
function ov8865_write
function ov8865_write_sequence
function ov8865_update_bits
function ov8865_sw_reset
function ov8865_sw_standby
function ov8865_chip_id_check
function ov8865_charge_pump_configure
function ov8865_mipi_configure
function ov8865_black_level_configure
function ov8865_isp_configure
function ov8865_mode_pll1_rate
function ov8865_mode_pll1_configure
function ov8865_mode_pll2_configure
function ov8865_mode_sclk_configure
function ov8865_mode_binning_configure
function ov8865_mode_black_level_configure
function ov8865_mode_configure
function ov8865_mode_mipi_clk_rate
function ov8865_exposure_configure
function ov8865_analog_gain_configure
function ov8865_red_balance_configure
function ov8865_blue_balance_configure
function ov8865_flip_vert_configure
function ov8865_flip_horz_configure
function ov8865_test_pattern_configure
function ov8865_vts_configure
function ov8865_state_mipi_configure
function ov8865_state_configure
function ov8865_state_init
function ov8865_sensor_init
function ov8865_sensor_power
function ov8865_s_ctrl
function ov8865_ctrls_init
function ov8865_s_stream
function ov8865_enum_mbus_code
function ov8865_mbus_format_fill
function ov8865_get_fmt

Annotated Snippet

struct ov8865_register_value {
	u16 address;
	u8 value;
	unsigned int delay_ms;
};

/*
 * PLL1 Clock Tree:
 *
 * +-< EXTCLK
 * |
 * +-+ pll_pre_div_half (0x30a [0])
 *   |
 *   +-+ pll_pre_div (0x300 [2:0], special values:
 *     |              0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 4, 7: 8)
 *     +-+ pll_mul (0x301 [1:0], 0x302 [7:0])
 *       |
 *       +-+ m_div (0x303 [3:0])
 *       | |
 *       | +-> PHY_SCLK
 *       | |
 *       | +-+ mipi_div (0x304 [1:0], special values: 0: 4, 1: 5, 2: 6, 3: 8)
 *       |   |
 *       |   +-+ pclk_div (0x3020 [3])
 *       |     |
 *       |     +-> PCLK
 *       |
 *       +-+ sys_pre_div (0x305 [1:0], special values: 0: 3, 1: 4, 2: 5, 3: 6)
 *         |
 *         +-+ sys_div (0x306 [0])
 *           |
 *           +-+ sys_sel (0x3032 [7], 0: PLL1, 1: PLL2)
 *             |
 *             +-+ sclk_sel (0x3033 [1], 0: sys_sel, 1: PLL2 DAC_CLK)
 *               |
 *               +-+ sclk_pre_div (0x3106 [3:2], special values:
 *                 |               0: 1, 1: 2, 2: 4, 3: 1)
 *                 |
 *                 +-+ sclk_div (0x3106 [7:4], special values: 0: 1)
 *                   |
 *                   +-> SCLK
 */

struct ov8865_pll1_config {
	unsigned int pll_pre_div_half;
	unsigned int pll_pre_div;
	unsigned int pll_mul;
	unsigned int m_div;
	unsigned int mipi_div;
	unsigned int pclk_div;
	unsigned int sys_pre_div;
	unsigned int sys_div;
};

/*
 * PLL2 Clock Tree:
 *
 * +-< EXTCLK
 * |
 * +-+ pll_pre_div_half (0x312 [4])
 *   |
 *   +-+ pll_pre_div (0x30b [2:0], special values:
 *     |              0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 4, 7: 8)
 *     +-+ pll_mul (0x30c [1:0], 0x30d [7:0])
 *       |
 *       +-+ dac_div (0x312 [3:0])
 *       | |
 *       | +-> DAC_CLK
 *       |
 *       +-+ sys_pre_div (0x30f [3:0])
 *         |
 *         +-+ sys_div (0x30e [2:0], special values:
 *           |          0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 3.5, 6: 4, 7:5)
 *           |
 *           +-+ sys_sel (0x3032 [7], 0: PLL1, 1: PLL2)
 *             |
 *             +-+ sclk_sel (0x3033 [1], 0: sys_sel, 1: PLL2 DAC_CLK)
 *               |
 *               +-+ sclk_pre_div (0x3106 [3:2], special values:
 *                 |               0: 1, 1: 2, 2: 4, 3: 1)
 *                 |
 *                 +-+ sclk_div (0x3106 [7:4], special values: 0: 1)
 *                   |
 *                   +-> SCLK
 */

struct ov8865_pll2_config {
	unsigned int pll_pre_div_half;
	unsigned int pll_pre_div;
	unsigned int pll_mul;

Annotation

Immediate include surface: `linux/clk.h`, `linux/delay.h`, `linux/device.h`, `linux/i2c.h`, `linux/mod_devicetable.h`, `linux/module.h`, `linux/of_graph.h`, `linux/pm_runtime.h`.
Detected declarations: `struct ov8865_register_value`, `struct ov8865_pll1_config`, `struct ov8865_pll2_config`, `struct ov8865_sclk_config`, `struct ov8865_pll_configs`, `struct ov8865_mode`, `struct ov8865_state`, `struct ov8865_ctrls`, `struct ov8865_sensor`, `enum extclk_rate`.
Atlas domain: Driver Families / drivers/media.
Implementation status: source implementation candidate.
Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.