drivers/media/i2c/saa711x_regs.h

Source file repositories/reference/linux-study-clean/drivers/media/i2c/saa711x_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/media/i2c/saa711x_regs.h
Extension
.h
Size
23045 bytes
Lines
561
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct saa711x_reg_descr {
	u8 reg;
	int count;
	char *name;
};

struct saa711x_reg_descr saa711x_regs[] = {
	/* REG COUNT NAME */
	{R_00_CHIP_VERSION,1,
	 "Chip version"},

	/* Video Decoder: R_01_INC_DELAY to R_1F_STATUS_BYTE_2_VD_DEC */

	/* Video Decoder - Frontend part: R_01_INC_DELAY to R_05_INPUT_CNTL_4 */
	{R_01_INC_DELAY,1,
	 "Increment delay"},
	{R_02_INPUT_CNTL_1,1,
	 "Analog input control 1"},
	{R_03_INPUT_CNTL_2,1,
	 "Analog input control 2"},
	{R_04_INPUT_CNTL_3,1,
	 "Analog input control 3"},
	{R_05_INPUT_CNTL_4,1,
	 "Analog input control 4"},

	/* Video Decoder - Decoder part: R_06_H_SYNC_START to R_1F_STATUS_BYTE_2_VD_DEC */
	{R_06_H_SYNC_START,1,
	 "Horizontal sync start"},
	{R_07_H_SYNC_STOP,1,
	 "Horizontal sync stop"},
	{R_08_SYNC_CNTL,1,
	 "Sync control"},
	{R_09_LUMA_CNTL,1,
	 "Luminance control"},
	{R_0A_LUMA_BRIGHT_CNTL,1,
	 "Luminance brightness control"},
	{R_0B_LUMA_CONTRAST_CNTL,1,
	 "Luminance contrast control"},
	{R_0C_CHROMA_SAT_CNTL,1,
	 "Chrominance saturation control"},
	{R_0D_CHROMA_HUE_CNTL,1,
	 "Chrominance hue control"},
	{R_0E_CHROMA_CNTL_1,1,
	 "Chrominance control 1"},
	{R_0F_CHROMA_GAIN_CNTL,1,
	 "Chrominance gain control"},
	{R_10_CHROMA_CNTL_2,1,
	 "Chrominance control 2"},
	{R_11_MODE_DELAY_CNTL,1,
	 "Mode/delay control"},
	{R_12_RT_SIGNAL_CNTL,1,
	 "RT signal control"},
	{R_13_RT_X_PORT_OUT_CNTL,1,
	 "RT/X port output control"},
	{R_14_ANAL_ADC_COMPAT_CNTL,1,
	 "Analog/ADC/compatibility control"},
	{R_15_VGATE_START_FID_CHG,  1,
	 "VGATE start FID change"},
	{R_16_VGATE_STOP,1,
	 "VGATE stop"},
	{R_17_MISC_VGATE_CONF_AND_MSB,  1,
	 "Miscellaneous VGATE configuration and MSBs"},
	{R_18_RAW_DATA_GAIN_CNTL,1,
	 "Raw data gain control",},
	{R_19_RAW_DATA_OFF_CNTL,1,
	 "Raw data offset control",},
	{R_1A_COLOR_KILL_LVL_CNTL,1,
	 "Color Killer Level Control"},
	{ R_1B_MISC_TVVCRDET, 1,
	  "MISC /TVVCRDET"},
	{ R_1C_ENHAN_COMB_CTRL1, 1,
	 "Enhanced comb ctrl1"},
	{ R_1D_ENHAN_COMB_CTRL2, 1,
	 "Enhanced comb ctrl1"},
	{R_1E_STATUS_BYTE_1_VD_DEC,1,
	 "Status byte 1 video decoder"},
	{R_1F_STATUS_BYTE_2_VD_DEC,1,
	 "Status byte 2 video decoder"},

	/* Component processing and interrupt masking part:  0x20h to R_2F_INTERRUPT_MASK_3 */
	/* 0x20 to 0x22 - Reserved */
	{R_23_INPUT_CNTL_5,1,
	 "Analog input control 5"},
	{R_24_INPUT_CNTL_6,1,
	 "Analog input control 6"},
	{R_25_INPUT_CNTL_7,1,
	 "Analog input control 7"},
	/* 0x26 to 0x28 - Reserved */
	{R_29_COMP_DELAY,1,
	 "Component delay"},

Annotation

Implementation Notes