drivers/media/pci/cx18/cx18-av-core.h

Source file repositories/reference/linux-study-clean/drivers/media/pci/cx18/cx18-av-core.h

File Facts

System
Linux kernel
Corpus path
drivers/media/pci/cx18/cx18-av-core.h
Extension
.h
Size
13640 bytes
Lines
377
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cx18_av_state {
	struct v4l2_subdev sd;
	struct v4l2_ctrl_handler hdl;
	struct v4l2_ctrl *volume;
	int radio;
	v4l2_std_id std;
	enum cx18_av_video_input vid_input;
	enum cx18_av_audio_input aud_input;
	u32 audclk_freq;
	int audmode;
	u32 rev;
	int is_initialized;

	/*
	 * The VBI slicer starts operating and counting lines, beginning at
	 * slicer line count of 1, at D lines after the deassertion of VRESET.
	 * This staring field line, S, is 6 (& 319) or 10 (& 273) for 625 or 525
	 * line systems respectively.  Sliced ancillary data captured on VBI
	 * slicer line M is inserted after the VBI slicer is done with line M,
	 * when VBI slicer line count is N = M+1.  Thus when the VBI slicer
	 * reports a VBI slicer line number with ancillary data, the IDID0 byte
	 * indicates VBI slicer line N.  The actual field line that the captured
	 * data comes from is
	 *
	 * L = M+(S+D-1) = N-1+(S+D-1) = N + (S+D-2).
	 *
	 * L is the line in the field, not frame, from which the VBI data came.
	 * N is the line reported by the slicer in the ancillary data.
	 * D is the slicer_line_delay value programmed into register 0x47f.
	 * S is 6 for 625 line systems or 10 for 525 line systems
	 * (S+D-2) is the slicer_line_offset used to convert slicer reported
	 * line counts to actual field lines.
	 */
	int slicer_line_delay;
	int slicer_line_offset;
};


/* Registers */
#define CXADEC_CHIP_TYPE_TIGER     0x837
#define CXADEC_CHIP_TYPE_MAKO      0x843

#define CXADEC_HOST_REG1           0x000
#define CXADEC_HOST_REG2           0x001

#define CXADEC_CHIP_CTRL           0x100
#define CXADEC_AFE_CTRL            0x104
#define CXADEC_PLL_CTRL1           0x108
#define CXADEC_VID_PLL_FRAC        0x10C
#define CXADEC_AUX_PLL_FRAC        0x110
#define CXADEC_PIN_CTRL1           0x114
#define CXADEC_PIN_CTRL2           0x118
#define CXADEC_PIN_CFG1            0x11C
#define CXADEC_PIN_CFG2            0x120

#define CXADEC_PIN_CFG3            0x124
#define CXADEC_I2S_MCLK            0x127

#define CXADEC_AUD_LOCK1           0x128
#define CXADEC_AUD_LOCK2           0x12C
#define CXADEC_POWER_CTRL          0x130
#define CXADEC_AFE_DIAG_CTRL1      0x134
#define CXADEC_AFE_DIAG_CTRL2      0x138
#define CXADEC_AFE_DIAG_CTRL3      0x13C
#define CXADEC_PLL_DIAG_CTRL       0x140
#define CXADEC_TEST_CTRL1          0x144
#define CXADEC_TEST_CTRL2          0x148
#define CXADEC_BIST_STAT           0x14C
#define CXADEC_DLL1_DIAG_CTRL      0x158
#define CXADEC_DLL2_DIAG_CTRL      0x15C

/* IR registers */
#define CXADEC_IR_CTRL_REG         0x200
#define CXADEC_IR_TXCLK_REG        0x204
#define CXADEC_IR_RXCLK_REG        0x208
#define CXADEC_IR_CDUTY_REG        0x20C
#define CXADEC_IR_STAT_REG         0x210
#define CXADEC_IR_IRQEN_REG        0x214
#define CXADEC_IR_FILTER_REG       0x218
#define CXADEC_IR_FIFO_REG         0x21C

/* Video Registers */
#define CXADEC_MODE_CTRL           0x400
#define CXADEC_OUT_CTRL1           0x404
#define CXADEC_OUT_CTRL2           0x408
#define CXADEC_GEN_STAT            0x40C
#define CXADEC_INT_STAT_MASK       0x410
#define CXADEC_LUMA_CTRL           0x414

#define CXADEC_BRIGHTNESS_CTRL_BYTE 0x414

Annotation

Implementation Notes