drivers/media/pci/cx18/cx18-scb.h

Source file repositories/reference/linux-study-clean/drivers/media/pci/cx18/cx18-scb.h

File Facts

System
Linux kernel
Corpus path
drivers/media/pci/cx18/cx18-scb.h
Extension
.h
Size
6770 bytes
Lines
267
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cx18_mdl_ent {
    u32 paddr;  /* Physical address of a buffer segment */
    u32 length; /* Length of the buffer segment */
};

struct cx18_scb {
	/* These fields form the System Control Block which is used at boot time
	   for localizing the IPC data as well as the code positions for all
	   processors. The offsets are from the start of this struct. */

	/* Offset where to find the Inter-Processor Communication data */
	u32 ipc_offset;
	u32 reserved01[7];
	/* Offset where to find the start of the CPU code */
	u32 cpu_code_offset;
	u32 reserved02[3];
	/* Offset where to find the start of the APU code */
	u32 apu_code_offset;
	u32 reserved03[3];
	/* Offset where to find the start of the HPU code */
	u32 hpu_code_offset;
	u32 reserved04[3];
	/* Offset where to find the start of the PPU code */
	u32 ppu_code_offset;
	u32 reserved05[3];

	/* These fields form Inter-Processor Communication data which is used
	   by all processors to locate the information needed for communicating
	   with other processors */

	/* Fields for CPU: */

	/* bit 0: 1/0 processor ready/not ready. Set other bits to 0. */
	u32 cpu_state;
	u32 reserved1[7];
	/* Offset to the mailbox used for sending commands from APU to CPU */
	u32 apu2cpu_mb_offset;
	/* Value to write to register SW1 register set (0xC7003100) after the
	   command is ready */
	u32 apu2cpu_irq;
	/* Value to write to register SW2 register set (0xC7003140) after the
	   command is cleared */
	u32 cpu2apu_irq_ack;
	u32 reserved2[13];

	u32 hpu2cpu_mb_offset;
	u32 hpu2cpu_irq;
	u32 cpu2hpu_irq_ack;
	u32 reserved3[13];

	u32 ppu2cpu_mb_offset;
	u32 ppu2cpu_irq;
	u32 cpu2ppu_irq_ack;
	u32 reserved4[13];

	u32 epu2cpu_mb_offset;
	u32 epu2cpu_irq;
	u32 cpu2epu_irq_ack;
	u32 reserved5[13];
	u32 reserved6[8];

	/* Fields for APU: */

	u32 apu_state;
	u32 reserved11[7];
	u32 cpu2apu_mb_offset;
	u32 cpu2apu_irq;
	u32 apu2cpu_irq_ack;
	u32 reserved12[13];

	u32 hpu2apu_mb_offset;
	u32 hpu2apu_irq;
	u32 apu2hpu_irq_ack;
	u32 reserved13[13];

	u32 ppu2apu_mb_offset;
	u32 ppu2apu_irq;
	u32 apu2ppu_irq_ack;
	u32 reserved14[13];

	u32 epu2apu_mb_offset;
	u32 epu2apu_irq;
	u32 apu2epu_irq_ack;
	u32 reserved15[13];
	u32 reserved16[8];

	/* Fields for HPU: */

	u32 hpu_state;
	u32 reserved21[7];

Annotation

Implementation Notes