drivers/media/pci/cx25821/cx25821-reg.h

Source file repositories/reference/linux-study-clean/drivers/media/pci/cx25821/cx25821-reg.h

File Facts

System
Linux kernel
Corpus path
drivers/media/pci/cx25821/cx25821-reg.h
Extension
.h
Size
76512 bytes
Lines
1579
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __CX25821_REGISTERS__
#define __CX25821_REGISTERS__

/* Risc Instructions */
#define RISC_CNT_INC	 0x00010000
#define RISC_CNT_RESET	 0x00030000
#define RISC_IRQ1		 0x01000000
#define RISC_IRQ2		 0x02000000
#define RISC_EOL		 0x04000000
#define RISC_SOL		 0x08000000
#define RISC_WRITE		 0x10000000
#define RISC_SKIP		 0x20000000
#define RISC_JUMP		 0x70000000
#define RISC_SYNC		 0x80000000
#define RISC_RESYNC		 0x80008000
#define RISC_READ		 0x90000000
#define RISC_WRITERM	 0xB0000000
#define RISC_WRITECM	 0xC0000000
#define RISC_WRITECR	 0xD0000000
#define RISC_WRITEC		 0x50000000
#define RISC_READC		 0xA0000000

#define RISC_SYNC_ODD		 0x00000000
#define RISC_SYNC_EVEN		 0x00000200
#define RISC_SYNC_ODD_VBI	 0x00000006
#define RISC_SYNC_EVEN_VBI	 0x00000207
#define RISC_NOOP			 0xF0000000

/*****************************************************************************
* ASB SRAM
 *****************************************************************************/
#define  TX_SRAM                   0x000000	/* Transmit SRAM */

/*****************************************************************************/
#define  RX_RAM                    0x010000	/* Receive SRAM */

/*****************************************************************************
* Application Layer (AL)
 *****************************************************************************/
#define  DEV_CNTRL2                0x040000	/* Device control */
#define  FLD_RUN_RISC              0x00000020

/* ***************************************************************************** */
#define  PCI_INT_MSK               0x040010	/* PCI interrupt mask */
#define  PCI_INT_STAT              0x040014	/* PCI interrupt status */
#define  PCI_INT_MSTAT             0x040018	/* PCI interrupt masked status */
#define  FLD_HAMMERHEAD_INT        (1 << 27)
#define  FLD_UART_INT              (1 << 26)
#define  FLD_IRQN_INT              (1 << 25)
#define  FLD_TM_INT                (1 << 28)
#define  FLD_I2C_3_RACK            (1 << 27)
#define  FLD_I2C_3_INT             (1 << 26)
#define  FLD_I2C_2_RACK            (1 << 25)
#define  FLD_I2C_2_INT             (1 << 24)
#define  FLD_I2C_1_RACK            (1 << 23)
#define  FLD_I2C_1_INT             (1 << 22)

#define  FLD_APB_DMA_BERR_INT      (1 << 21)
#define  FLD_AL_WR_BERR_INT        (1 << 20)
#define  FLD_AL_RD_BERR_INT        (1 << 19)
#define  FLD_RISC_WR_BERR_INT      (1 << 18)
#define  FLD_RISC_RD_BERR_INT      (1 << 17)

#define  FLD_VID_I_INT             (1 << 8)
#define  FLD_VID_H_INT             (1 << 7)
#define  FLD_VID_G_INT             (1 << 6)
#define  FLD_VID_F_INT             (1 << 5)
#define  FLD_VID_E_INT             (1 << 4)
#define  FLD_VID_D_INT             (1 << 3)
#define  FLD_VID_C_INT             (1 << 2)
#define  FLD_VID_B_INT             (1 << 1)
#define  FLD_VID_A_INT             (1 << 0)

/* ***************************************************************************** */
#define  VID_A_INT_MSK             0x040020	/* Video A interrupt mask */
#define  VID_A_INT_STAT            0x040024	/* Video A interrupt status */
#define  VID_A_INT_MSTAT           0x040028	/* Video A interrupt masked status */
#define  VID_A_INT_SSTAT           0x04002C	/* Video A interrupt set status */

/* ***************************************************************************** */
#define  VID_B_INT_MSK             0x040030	/* Video B interrupt mask */
#define  VID_B_INT_STAT            0x040034	/* Video B interrupt status */
#define  VID_B_INT_MSTAT           0x040038	/* Video B interrupt masked status */
#define  VID_B_INT_SSTAT           0x04003C	/* Video B interrupt set status */

/* ***************************************************************************** */
#define  VID_C_INT_MSK             0x040040	/* Video C interrupt mask */
#define  VID_C_INT_STAT            0x040044	/* Video C interrupt status */
#define  VID_C_INT_MSTAT           0x040048	/* Video C interrupt masked status */
#define  VID_C_INT_SSTAT           0x04004C	/* Video C interrupt set status */

Annotation

Implementation Notes