drivers/media/pci/cx25821/cx25821-sram.h

Source file repositories/reference/linux-study-clean/drivers/media/pci/cx25821/cx25821-sram.h

File Facts

System
Linux kernel
Corpus path
drivers/media/pci/cx25821/cx25821-sram.h
Extension
.h
Size
9264 bytes
Lines
248
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ATHENA_SRAM_H__
#define __ATHENA_SRAM_H__

/* #define RX_SRAM_START_SIZE        = 0;  //  Start of reserved SRAM */
#define VID_CMDS_SIZE             80	/* Video CMDS size in bytes */
#define AUDIO_CMDS_SIZE           80	/* AUDIO CMDS size in bytes */
#define MBIF_CMDS_SIZE            80	/* MBIF  CMDS size in bytes */

/* #define RX_SRAM_POOL_START_SIZE   = 0;  //  Start of usable RX SRAM for buffers */
#define VID_IQ_SIZE               64	/* VID instruction queue size in bytes */
#define MBIF_IQ_SIZE              64
#define AUDIO_IQ_SIZE             64	/* AUD instruction queue size in bytes */

#define VID_CDT_SIZE              64	/* VID cluster descriptor table size in bytes */
#define MBIF_CDT_SIZE             64	/* MBIF/HBI cluster descriptor table size in bytes */
#define AUDIO_CDT_SIZE            48	/* AUD cluster descriptor table size in bytes */

/* #define RX_SRAM_POOL_FREE_SIZE    = 16; //  Start of available RX SRAM */
/* #define RX_SRAM_END_SIZE          = 0;  //  End of RX SRAM */

/* #define TX_SRAM_POOL_START_SIZE   = 0;  //  Start of transmit pool SRAM */
/* #define MSI_DATA_SIZE             = 64; //  Reserved (MSI Data, RISC working stora */

#define VID_CLUSTER_SIZE          1440	/* VID cluster data line */
#define AUDIO_CLUSTER_SIZE        128	/* AUDIO cluster data line */
#define MBIF_CLUSTER_SIZE         1440	/* MBIF/HBI cluster data line */

/* #define TX_SRAM_POOL_FREE_SIZE    = 704;    //  Start of available TX SRAM */
/* #define TX_SRAM_END_SIZE          = 0;      //  End of TX SRAM */

/* Receive SRAM */
#define RX_SRAM_START             0x10000
#define VID_A_DOWN_CMDS           0x10000
#define VID_B_DOWN_CMDS           0x10050
#define VID_C_DOWN_CMDS           0x100A0
#define VID_D_DOWN_CMDS           0x100F0
#define VID_E_DOWN_CMDS           0x10140
#define VID_F_DOWN_CMDS           0x10190
#define VID_G_DOWN_CMDS           0x101E0
#define VID_H_DOWN_CMDS           0x10230
#define VID_A_UP_CMDS             0x10280
#define VID_B_UP_CMDS             0x102D0
#define VID_C_UP_CMDS             0x10320
#define VID_D_UP_CMDS             0x10370
#define VID_E_UP_CMDS             0x103C0
#define VID_F_UP_CMDS             0x10410
#define VID_I_UP_CMDS             0x10460
#define VID_J_UP_CMDS             0x104B0
#define AUD_A_DOWN_CMDS           0x10500
#define AUD_B_DOWN_CMDS           0x10550
#define AUD_C_DOWN_CMDS           0x105A0
#define AUD_D_DOWN_CMDS           0x105F0
#define AUD_A_UP_CMDS             0x10640
#define AUD_B_UP_CMDS             0x10690
#define AUD_C_UP_CMDS             0x106E0
#define AUD_E_UP_CMDS             0x10730
#define MBIF_A_DOWN_CMDS          0x10780
#define MBIF_B_DOWN_CMDS          0x107D0
#define DMA_SCRATCH_PAD           0x10820	/* Scratch pad area from 0x10820 to 0x10B40 */

/* #define RX_SRAM_POOL_START        = 0x105B0; */

#define VID_A_IQ                  0x11000
#define VID_B_IQ                  0x11040
#define VID_C_IQ                  0x11080
#define VID_D_IQ                  0x110C0
#define VID_E_IQ                  0x11100
#define VID_F_IQ                  0x11140
#define VID_G_IQ                  0x11180
#define VID_H_IQ                  0x111C0
#define VID_I_IQ                  0x11200
#define VID_J_IQ                  0x11240
#define AUD_A_IQ                  0x11280
#define AUD_B_IQ                  0x112C0
#define AUD_C_IQ                  0x11300
#define AUD_D_IQ                  0x11340
#define AUD_E_IQ                  0x11380
#define MBIF_A_IQ                 0x11000
#define MBIF_B_IQ                 0x110C0

#define VID_A_CDT                 0x10C00
#define VID_B_CDT                 0x10C40
#define VID_C_CDT                 0x10C80
#define VID_D_CDT                 0x10CC0
#define VID_E_CDT                 0x10D00
#define VID_F_CDT                 0x10D40
#define VID_G_CDT                 0x10D80
#define VID_H_CDT                 0x10DC0
#define VID_I_CDT                 0x10E00
#define VID_J_CDT                 0x10E40

Annotation

Implementation Notes