drivers/media/pci/intel/ipu6/ipu6.h

Source file repositories/reference/linux-study-clean/drivers/media/pci/intel/ipu6/ipu6.h

File Facts

System
Linux kernel
Corpus path
drivers/media/pci/intel/ipu6/ipu6.h
Extension
.h
Size
10608 bytes
Lines
343
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ipu6_device {
	struct pci_dev *pdev;
	struct list_head devices;
	struct ipu6_bus_device *isys;
	struct ipu6_bus_device *psys;
	struct ipu6_buttress buttress;

	const struct firmware *cpd_fw;
	const char *cpd_fw_name;
	u32 cpd_metadata_cmpnt_size;

	void __iomem *base;
	bool need_ipc_reset;
	bool secure_mode;
	u8 hw_ver;
	bool bus_ready_to_probe;
};

#define IPU6_ISYS_NAME "isys"
#define IPU6_PSYS_NAME "psys"

#define IPU6_MMU_MAX_DEVICES		4
#define IPU6_MMU_ADDR_BITS		32
/* The firmware is accessible within the first 2 GiB only in non-secure mode. */
#define IPU6_MMU_ADDR_BITS_NON_SECURE	31

#define IPU6_MMU_MAX_TLB_L1_STREAMS	32
#define IPU6_MMU_MAX_TLB_L2_STREAMS	32
#define IPU6_MAX_LI_BLOCK_ADDR		128
#define IPU6_MAX_L2_BLOCK_ADDR		64

#define IPU6SE_ISYS_NUM_STREAMS          IPU6SE_NONSECURE_STREAM_ID_MAX
#define IPU6_ISYS_NUM_STREAMS            IPU6_NONSECURE_STREAM_ID_MAX

/*
 * To maximize the IOSF utlization, IPU6 need to send requests in bursts.
 * At the DMA interface with the buttress, there are CDC FIFOs with burst
 * collection capability. CDC FIFO burst collectors have a configurable
 * threshold and is configured based on the outcome of performance measurements.
 *
 * isys has 3 ports with IOSF interface for VC0, VC1 and VC2
 * psys has 4 ports with IOSF interface for VC0, VC1w, VC1r and VC2
 *
 * Threshold values are pre-defined and are arrived at after performance
 * evaluations on a type of IPU6
 */
#define IPU6_MAX_VC_IOSF_PORTS		4

/*
 * IPU6 must configure correct arbitration mechanism related to the IOSF VC
 * requests. There are two options per VC0 and VC1 - > 0 means rearbitrate on
 * stall and 1 means stall until the request is completed.
 */
#define IPU6_BTRS_ARB_MODE_TYPE_REARB	0
#define IPU6_BTRS_ARB_MODE_TYPE_STALL	1

/* Currently chosen arbitration mechanism for VC0 */
#define IPU6_BTRS_ARB_STALL_MODE_VC0	\
			IPU6_BTRS_ARB_MODE_TYPE_REARB

/* Currently chosen arbitration mechanism for VC1 */
#define IPU6_BTRS_ARB_STALL_MODE_VC1	\
			IPU6_BTRS_ARB_MODE_TYPE_REARB

/*
 * MMU Invalidation HW bug workaround by ZLW mechanism
 *
 * Old IPU6 MMUV2 has a bug in the invalidation mechanism which might result in
 * wrong translation or replication of the translation. This will cause data
 * corruption. So we cannot directly use the MMU V2 invalidation registers
 * to invalidate the MMU. Instead, whenever an invalidate is called, we need to
 * clear the TLB by evicting all the valid translations by filling it with trash
 * buffer (which is guaranteed not to be used by any other processes). ZLW is
 * used to fill the L1 and L2 caches with the trash buffer translations. ZLW
 * or Zero length write, is pre-fetch mechanism to pre-fetch the pages in
 * advance to the L1 and L2 caches without triggering any memory operations.
 *
 * In MMU V2, L1 -> 16 streams and 64 blocks, maximum 16 blocks per stream
 * One L1 block has 16 entries, hence points to 16 * 4K pages
 * L2 -> 16 streams and 32 blocks. 2 blocks per streams
 * One L2 block maps to 1024 L1 entries, hence points to 4MB address range
 * 2 blocks per L2 stream means, 1 stream points to 8MB range
 *
 * As we need to clear the caches and 8MB being the biggest cache size, we need
 * to have trash buffer which points to 8MB address range. As these trash
 * buffers are not used for any memory transactions, we need only the least
 * amount of physical memory. So we reserve 8MB IOVA address range but only
 * one page is reserved from physical memory. Each of this 8MB IOVA address
 * range is then mapped to the same physical memory page.
 */

Annotation

Implementation Notes