drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c

Source file repositories/reference/linux-study-clean/drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c

File Facts

System
Linux kernel
Corpus path
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
Extension
.c
Size
6283 bytes
Lines
243
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013--2024 Intel Corporation
 */

#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/io.h>

#include "ipu6-bus.h"
#include "ipu6-isys.h"
#include "ipu6-isys-csi2.h"
#include "ipu6-platform-isys-csi2-reg.h"

/* only use BB0, BB2, BB4, and BB6 on PHY0 */
#define IPU6SE_ISYS_PHY_BB_NUM		4
#define IPU6SE_ISYS_PHY_0_BASE		0x10000

#define PHY_CPHY_DLL_OVRD(x)		(0x100 + 0x100 * (x))
#define PHY_CPHY_RX_CONTROL1(x)		(0x110 + 0x100 * (x))
#define PHY_DPHY_CFG(x)			(0x148 + 0x100 * (x))
#define PHY_BB_AFE_CONFIG(x)		(0x174 + 0x100 * (x))

/*
 * use port_cfg to configure that which data lanes used
 * +---------+     +------+ +-----+
 * | port0 x4<-----|      | |     |
 * |         |     | port | |     |
 * | port1 x2<-----|      | |     |
 * |         |     |      <-| PHY |
 * | port2 x4<-----|      | |     |
 * |         |     |config| |     |
 * | port3 x2<-----|      | |     |
 * +---------+     +------+ +-----+
 */
static const unsigned int csi2_port_cfg[][3] = {
	{0, 0, 0x1f}, /* no link */
	{4, 0, 0x10}, /* x4 + x4 config */
	{2, 0, 0x12}, /* x2 + x2 config */
	{1, 0, 0x13}, /* x1 + x1 config */
	{2, 1, 0x15}, /* x2x1 + x2x1 config */
	{1, 1, 0x16}, /* x1x1 + x1x1 config */
	{2, 2, 0x18}, /* x2x2 + x2x2 config */
	{1, 2, 0x19} /* x1x2 + x1x2 config */
};

/* port, nlanes, bbindex, portcfg */
static const unsigned int phy_port_cfg[][4] = {
	/* sip0 */
	{0, 1, 0, 0x15},
	{0, 2, 0, 0x15},
	{0, 4, 0, 0x15},
	{0, 4, 2, 0x22},
	/* sip1 */
	{2, 1, 4, 0x15},
	{2, 2, 4, 0x15},
	{2, 4, 4, 0x15},
	{2, 4, 6, 0x22}
};

static void ipu6_isys_csi2_phy_config_by_port(struct ipu6_isys *isys,
					      unsigned int port,
					      unsigned int nlanes)
{
	struct device *dev = &isys->adev->auxdev.dev;
	void __iomem *base = isys->adev->isp->base;
	unsigned int bbnum;
	u32 val, reg, i;

	dev_dbg(dev, "port %u with %u lanes", port, nlanes);

	/* only support <1.5Gbps */
	for (i = 0; i < IPU6SE_ISYS_PHY_BB_NUM; i++) {
		/* cphy_dll_ovrd.crcdc_fsm_dlane0 = 13 */
		reg = IPU6SE_ISYS_PHY_0_BASE + PHY_CPHY_DLL_OVRD(i);
		val = readl(base + reg);
		val |= FIELD_PREP(GENMASK(6, 1), 13);
		writel(val, base + reg);

		/* cphy_rx_control1.en_crc1 = 1 */
		reg = IPU6SE_ISYS_PHY_0_BASE + PHY_CPHY_RX_CONTROL1(i);
		val = readl(base + reg);
		val |= BIT(31);
		writel(val, base + reg);

		/* dphy_cfg.reserved = 1, .lden_from_dll_ovrd_0 = 1 */
		reg = IPU6SE_ISYS_PHY_0_BASE + PHY_DPHY_CFG(i);
		val = readl(base + reg);
		val |= BIT(25) | BIT(26);

Annotation

Implementation Notes